Consider the following later stack (it's only the top 3 layers of an 8 layer board)

  1. Top Signal Layer
  2. Plane
  3. Signal Layer

I have a high frequency trace that is being routed on the top layer and I need to route to layer 3.

I was reading in ( I don't even remember which book anymore), that the return path will only be the surface of the plane due to the skin effect, and so the return path for layer 1 is the top of the plane and the return path for the layer 3 is the bottom of the plane.

In order for the return path on the top plane get to the bottom plane when the signal goes from layer 1 to layer 3, I need to provide some controlled way for the return current current to get there.

There were a few ways, but one of them was to use an anti pad. From the image in the book, it looks like a via with a giant hole surrounding the barrel of the via.

What is the physical geometry that makes an anti pad ? How do I make one in CAD ?


Electromagnetic Compatibility Engineering - Henry Ott

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  • 1
    \$\begingroup\$ The clip from Ott's book is saying basically (with more detail) what I said in my last paragraph. It applies when you are transitioning between layers that aren't referenced to the same plane layer, like a transition from L1 to L8, for example. \$\endgroup\$ – The Photon Apr 30 '15 at 6:08
  • \$\begingroup\$ It would help to know your operating frequency (or rise/fall-time if you're doing a digital design). \$\endgroup\$ – The Photon Apr 30 '15 at 6:09
  • \$\begingroup\$ Design requirement changed, and so looking into new microcontroller. It would be in the range between 100Mhz-200Mhz, and I have some devices with 2-3ns rise/fall times. \$\endgroup\$ – efox29 Apr 30 '15 at 6:18
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    \$\begingroup\$ As shown in your new image, routing "on two layers that are adjacent to the same plane" is the second-best way to route your signal. Your cad tool will automatically make an antipad around the signal via to avoid shorting to the plane. \$\endgroup\$ – The Photon Apr 30 '15 at 6:24
  • \$\begingroup\$ @ThePhoton I understand what the antipad is now. But with regards to your comment that the a via is not required, under what conditions is not required ? Trying to understand from a best design practice point of view and an experienced practical side as well. \$\endgroup\$ – efox29 Apr 30 '15 at 6:28

This is a case of a lot of ado about nothing, almost. Ott's style is unfortunately overly verbose at times, and the drawings are, frankly, atrociously confusing. An anti-pad is simply the hole in the plane, and is already there in any sane CAD. The only question is what size does the hole need to be, other than due to board manufacturability concerns.

First of all, you must calculate the skin depth for your signal, and then decide if skin effects play a role in the propagation of that signal's return current on the plane of a given thickness.

If they do, then the cylindrical surface of the hole in the plane is where the return signal flows, due to skin effect. You may wish to make the hole (the anti-pad) larger than the default, to lower the resistance and perhaps also inductance seen by the return signal.

  1. Are you really making a 3-layer board? That's usually a bad idea for symmetry reasons. The board will tend to warp. If you're actually making a 4-layer board but you only mentioned three of the layers, it's still better to balance plane and signal layers. So you'd rather have 1. signal 2. plane 3. plane 4. signal, for example.

  2. What frequency are you operating at. I'm not going to do the calculations but if you are working below 100 MHz, I wouldn't worry too much about skin effect (the reason that "the return path for layer 1 is the top of the plane and the return path for the layer 3 is the bottom of the plane").

  3. Even if skin effect is an issue, there is a very low impedance path from the top of the plane to the bottom of the plane --- just go through the copper.

  4. An antipad is just a void in the plane layer around a via. It prevents the plane from being short-circuited to the via. An antipad doesn't make a path for current to flow anywhere. It is a void that prevents current flowing where you don't want it to.

  5. Most CAD tools will automatically make an antipad whenever you place a via that isn't associated with the same net as the plane. If they didn't, every via would short circuit to every plane.

  6. Planes are layers where there is copper everywhere except where you place a feature on the layer. If, after what I've said so far, you still want to manually place an antipad, you can do it by just placing a circular (or whatever shape you want) feature onto the plane layer in your CAD tool.

Note: If you do switch to a 4-layer stack-up and you want to have a high-speed signal transition from L1 to L4, then you do want to provide a way for the return current to transition from L2 to L3. Since L2 and L3 are usually power and ground, you'd usually do that using a capacitor connecting those two nets, rather than providing a dc current path. If your operating frequency is below 1 GHz, the path from L2 to an outer layer, through the capacitor, and then back down to L3 is usually acceptable, although it does introduce an inductive discontinuity in the transmission line. If you really need to nail the signal integrity you'd have to get into some detailed simulations to optimize the design.

  • \$\begingroup\$ Its not a 3 layer board. It's an 8 layer board. I only mentioned the first 3. The signal is over 100Mhz. In this book, it says that stiching caps should be used as a last resort if the other methods are not possible. What criteria or conditions would stitching caps are "ok" to use? \$\endgroup\$ – efox29 Apr 30 '15 at 6:14
  • \$\begingroup\$ Stitching caps would be okay if you can tolerate the inductive discontinuity (Ott says 5 mH, and that sounds reasonable to me too). Also if you're routing over power planes remember to watch out for routing over plane splits. \$\endgroup\$ – The Photon Apr 30 '15 at 6:16
  • \$\begingroup\$ But if your signal transitions from L1 to L3 and L2 is ground, you don't need any capacitor or even a via --- current has no problem flowing from the top of L2 to the bottom of L2. \$\endgroup\$ – The Photon Apr 30 '15 at 6:18
  • \$\begingroup\$ I actually added the wrong picture the first time around. I added a new picture. What you say, seems to contradict what I read. This section doesn't specify at what frequencies this is relevant. \$\endgroup\$ – efox29 Apr 30 '15 at 6:23

Others have already explained that an anti-pad is a copper keepout area surrounding a structure, usually a via but it could also be a via. The intention is to increase the copper to copper clearance on the layer of choice.

However, I don't think anyone has answered your high frequency question regarding skin effect of return currents. I agree that the return current path is critical. Usually we would like the most direct path between the signal source and sink. However, in practice, the return current path will the the path of least impedance. In practice for electromagnetic reasons not explained here, this is usually in parallel to the signal's current path. That is the return path doesn't usually obey Pythagorean theorem.

This is where via stitching comes in. As you said, the return current must get from the top of the plane to the bottom. The best way to do that is to place a parallel via for ground right next to the signal via. We could even put multiple vias to reduce the via's impedance to the return current path. Ultimately, we want to reduce the distance/impedance the return current needs to find it's way back home.

Here's an example 10129181 Amphenol FCI of a 25 gigabit Ethernet backplane connector. Notice the recommended layout. There are pairs of signals for each Ethernet lane. Next to every signal via is another via. This is for ground. This reduces the return current path distance and also has some EMI/crosstalk shielding benefits. This is much better than having the ground signals bunched up together.

Here's an example 09062216883 Harting of a connector that a schematic designer could mess up. This connector offers beautiful power pins. However, if the designer doesn't allocate stitching ground pins on the signal side, the return current path will be forced to travel extra distance through one of the 5 power connectors.

There are more differences between these two connectors that make them suited for different signals but I only hope to answer it as it relates to return current paths.


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