Is there a common netlist format that is portable between different schematic/pcb/EDA/CAD tools, and if so where is the format or reference so I can implement it?
If not, does each package implement it differently, or are there a few standards that, if implemented, might give greater compatibility with a broad range of tools?
EDIF - Electronic Design Interchange Format - is a vendor neutral format in which to store Electronic netlists and schematics. It was one of the first attempts to establish a neutral data exchange format for the electronic design automation (EDA) industry.
See http://en.wikipedia.org/wiki/EDIF for more information and links.
I have not seen any standards. Each package implements their own format. Fortunately the format is very simple making it easy to translate between packages.
For example the gEDA netlist consists of records in the following format --
NETNAME REFDES-PIN REFDES-PIN ...
here is a sample from one of my boards --
unnamed_net39 J28-3 U11-12
unnamed_net38 J28-1 J16-2 J27-1
GND J16-3 C16-2 J15-3 C15-2
You could easily read this netlist file into a data structure and translate it to a different format.
If they are saved in ASCII form it is quite easy to convert them, I can import most formats into the Pulsonix PCB software I use. The only awkward one is Eagle; Eagle schematics, PCBs and libraries have to be converted by a specially written ULP.
I haven't seen a standard format anywhere, either. However, as others have mentioned, netlist formats are very simple and usually text-based, and thus trivial to translate between various forms.
A netlist is simply a list of nets (wires), with a list of ports (pins of components) that attach on each wire. Although the details differ, it's all a variation of the same theme. In the past I've written several scripts in Perl and Python that easily manipulate netlists. As a matter of fact, netlist files are a great exercise in beginner-level text processing.
Honestly, if you really want a netlist format that will in practice work with just about any tool, you have just two serious choices:
Yes, these are full-blown hardware description languages, and using them as a netlist format could be considered overkill. However, it is very easy, and if a tool spits out simple, structural VHDL or Verilog, you can be quite confident that you'll be able to pull the design back into just about any other EDA tool.
As a side benefit, most other netlist formats (e.g. EDIF) need to have an externally defined set of primitives -- either something vendor specific, or something like LPM. With VHDL and Verilog, the lowest level leaves (primitives) can just be whatever you want (e.g. synthesizable RTL code, simulation models, black boxes, etc).
However, if you absolutely must have an actual netlist format, I second the suggestion to use the gnetlist format, which can then be converted to many other formats.
Google and Antmicro recently launched the FPGA Interchange format which includes a standard for describing logical and physical netlists.
