In above figure, "LDO layout A" and "LDO layout B" are indicative PCB layouts of an LDO - focusing on its output capacitor.
- "A" refers to a layout where trace from OUT pin of the LDO hits C1 first and then goes to the load VCC pin.
- "B" refers to a layout where two separate traces originate from the OUT pin - one going to C1, and the other going to the load VCC pin.
The LDO is LD1117-3.3V and the max current consumed by the load is 100mA. C1 is an electrolytic capacitor. The width of the power traces is 32 Mil. The length of the trace from C1 to LDO-OUT pin in layout "B" is ~200 Mil. The VCC pin (load) has its own 0.1uf decoupling cap, placed closed to the VCC pin.
Are there any drawbacks of using layout "B" (two separate traces from the OUT pin of LDO)? I would have preferred "A" but due to board constraints, if I have to go with "B", what would be the consequences?