1
\$\begingroup\$

I have the below timer 5 interrupt vector that is not entered, even when both the corresponding Interrupt enable bit for timer 5 is set, and the corresponding interrupt flag for timer 5 is set.

Here is my interrupt vector handler:

void __ISR(_TIMER_5_VECTOR,IPL4SOFT) _T5Interrupt(void)
{
    PORTDbits.RD2 = 1;  // << -- LED will light when here. 
    T4CONbits.ON = 0;
    TMR4 = 0;
    TMR5 = 0;
    Global_TimeOut = 1;
    IFS0bits.T5IF = 0;
}

My global interrupts are set to accept multi-vector interrupts and is initialized as follows:

void Init_Global_Interrupts(void)
{
    // Initializing Global Interrupts
    //INTCON
    // 16 Single Vector is not presented with a shadow register set
    INTCONbits.SS0 = 0;
    // 12 Interrupt Controller configured for multi vectored mode
    INTCONbits.MVEC = 1;
    // 10 - 8 Disables interrupt proximity timer
    INTCONbits.TPC = 0;
    // 4 External interrupt 0 falling edge interrupt
    INTCONbits.INT0EP = 0;
    // 4 External interrupt 1 falling edge interrupt
    INTCONbits.INT1EP = 0;
    // 4 External interrupt 2 falling edge interrupt
    INTCONbits.INT2EP = 0;
    // 4 External interrupt 3 falling edge interrupt
    INTCONbits.INT3EP = 0;
    // 4 External interrupt 4 falling edge interrupt
    INTCONbits.INT4EP = 0;
}

Timer 4 and timer 5 is being used in 32 bit mode. As the data sheet states, in this configuration, it is timer 5 interrupts that is used:

void Init_Timer4_5(void)
{
    // 15 - Timer 4 is off
    T4CONbits.ON = 0;
    // 13 - Continue operation when device enters idle mode
    T4CONbits.SIDL = 0;
    // 7 - Gated time accumulation is disabled
    T4CONbits.TGATE = 0;
    // 6 - 4 - 1:8 prescale to achieve a 1uS unit time
    T4CONbits.TCKPS = 3;
    // 3 - Timer 4 and 5 set for 32 bit operation
    T4CONbits.T32 = 1;
    // 1 - Use internal Peripheral clock
    T4CONbits.TCS = 0;

    // Setting Timer 5 priority to level 4 of 7
    IPC5bits.T5IP = 4;
    // setting timer 5 sub priority to level 1 of 3
    IPC5bits.T5IS = 1;
    // Clear timer interrupt flag
    IFS0bits.T5IF = 0;
    // Enable timer interrupts
    IEC0bits.T5IE = 1;
}

The timers are started with the following function:

void Time_Out(unsigned int uTime)
{
    T4CONbits.ON = 0;
    TMR4 = 0;
    TMR5 = 0;
    Global_TimeOut = 0;

    PR4 = uTime;

    T4CONbits.ON = 1;
}

As far as I can tell, I have done everything necessary.

Let me know if you require any additional information.

\$\endgroup\$
2
\$\begingroup\$

I also had to turn on the global interrupts. Its somewhat of a hidden bit.

It is a bit within the Coprocessor status register, and you can enable it by using:

__asm__("EI");

or disable it by using:

__asm__("DI");
\$\endgroup\$
0
\$\begingroup\$

This is the sample that works, I'm pasting it from one of my current projects:

int main(void) {

T2CONbits.T32 = 1;    //32-bit timer
T2CONbits.ON = 1;    //start
PR2 = 0xFFFF;
PR3 = 0xFFFF;
IPC3bits.T3IP = 1;    //interrupt priority
IFS0CLR = _IFS0_T3IF_MASK;
IEC0SET = _IEC0_T3IE_MASK;          //Timer 3 interrupt (for 2-3 pair

while(1);

}

//counts Timer2-3 overflows.
extern "C" void __ISR(_TIMER_3_VECTOR, IPL1AUTO) t23ISR() {

Rolls_t23++;                //increment rollover counter
IFS0CLR = _IFS0_T3IF_MASK;    //clear interrupt
}

You should be able to paste it into MPLABX, set the breakpoint inside the ISR and see the program hitting this breakpoint every once in a while (check period and decrease if necessary). If you don't see it make sure your conf.bits are right and the micro is actually executing the code (set another breakpoint to while(1), for example).

\$\endgroup\$
  • \$\begingroup\$ @OlgeMazurov This code did not work for me, so I think there is a problem with my setup, I will update the question momentarily to include more information on the setup. \$\endgroup\$ – Volcano May 4 '15 at 19:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.