VHDL and Verilog are the HDLs of the day. What are the advantages of either for someone who has no experience with HDLs at all?
I can't tell you which to learn, but here's some contrasting points (from a very VHDL-centric user, but I've tried to be as fair as possible!), which may help you make a choice based on your own preferences in terms of development style:
And keep in mind the famous quote which goes along the lines of "I prefer whichever of the two I'm not currently using" (sorry, I can't recall who actually wrote this - possibly Janick Bergeron?)
- more verbose
- very deterministic
- non-C-like syntax (and mindset)
Lots of compilation errors to start with, but then mostly works how you expect. This can lead to a very steep feeling learning curve (along with the unfamiliar syntax)
- more concise
- only deterministic if you follow some rules carefully
- more C-like syntax (and mindset)
Errors are found later in simulation - the learning curve to "feeling like getting something done" is shallower, but goes on longer (if that's the right metaphor?)
Also in Verilog's favour is that high-end verification is leaning more and more to SystemVerilog which is a huge extension to Verilog. But the high-end tools can also combine VHDL synthesis code with SystemVerilog verification code.
For another approach entirely: MyHDL - you get all the power of Python as a verification language with a set of synthesis extensions from which you can generate either VHDL or Verilog.
Or Cocotb - all the power of Python as a verification language, with your synthesisable code still written in whichever HDL you decided to learn (ie VHDL or Verilog).
I learned both the same week. VHDL is like ADA/Pascal and Verilog is like C. VHDL is more verbose and more painful to get a compile, but once you get a compile your chances at success are better. At least that is what I found. Verilog, like C, is quite content at letting you shoot yourself in the foot. Some industries like aerospace/govt lean toward VHDL, others lean toward Verilog. The problem I find with both is the test bench capabilities, and when trying to learn and trying to get from simulation to silicon/FPGA writing synthesizable only code is another level of education.
There is a language I really like called CDL. It is strictly synthesizable, you write your test benches in other ways, it generates synthesizable Verilog which you can take into other tools. Unfortunately the CDL docs are lacking, I hope to get some samples out in the world to show how much easier it is to use than either Verilog or VHDL, but just dont have that done. It comes with its own sim/test environment. With CDL and GTKWave you can do a considerable amount of work.
Another tool called Verilator, is fairly rigid in keeping your Verilog clean. It is a free Verilog simulator with a very easy way to attach to the sim or create test benches in C/C++. You can use Verilog as well, doesn't limit you there. There is Icarus Verilog as well, which is bigger and more well known, but I would recommend Verilator if you want to learn Verilog. For VHDL there is GHDL, my experience with it was not as good as Verilator, but at least there is a free tool for trying to get your feet wet. If you have software programming experience you are likely to pick up and enjoy Verilog faster than VHDL.
I definitely agree with Leon, try both. fpga4fun and other web pages has some good info and some of those pages will give you both the Verilog and VHDL equivalents for the topic they are discussing. I find pages like those the most useful for comparing the two languages. If using an HDL is something you want to do in your career, I recommend having at least some capabilities with both, maybe really good with one but don't be completely unable to use the other.
Many holy wars have been fought over this. One particular disadvantage of Verilog is its non-deterministic behavior. http://www.sigasi.com/content/verilogs-major-flaw
Both have advantages and disadvantages. VHDL is more academic, verbose and complex. You have to write more code, but the rigor means it's more likely to work. Verilog is simpler for typical digital design, but makes it easier to create tricky bugs. VHDL is more common at universities. Verilog is more common in big semiconductor companies.
Usually the choice of one or the other is driven by the tools you are using. Some of the popular FPGA tools do better with VHDL. Some popular ASIC tools do better with Verilog. So, which is better depends on what you want to do with it.
Say you want to build small projects using the Altera FPGAs that are popular in EE schools. The free tools support both HDLs. But you may find the user community is mostly using VHDL. There will be more example code, reusable modules, etc. if you opt for that language.
Conversely, if you intend to work in a big company doing serious chip design work, almost all of them use Verilog these days. The heavy-duty synthesis, simulation and verification tools are optimized for Verilog. And lately, SystemVerilog - extensions to Verilog to support high-level system design and verification.
More discussion here and useful links here:
For a beginner/hobbyist, the best advice is to decide what chips you want to play with, and see what examples the vendor provides. Use that. Once you're an experienced digital designer, learning the other language will only take a few days.
Short answer: use SystemVerilog, but learn also VHDL. Avoid Verilog-2001 if you can.
Very long answer: for the moment, I assume by Verilog you mean Verilog-2001 which is probably what also most other answers assume. The best suggestion would probably be to learn both, but use neither (more on this at the end of the answer). The main differences can be resumed in the following:
- Verilog-2001 is concise, while VHDL is (very, very, very) verbose
- Verilog-2001 supports very low level constructs that are not supported by VHDL (but you won't have to use them for typical register-transfer level (RTL) design
- VHDL is more strongly typed, which typically makes it much easier to detect errors early
- VHDL is much more expressive than Verilog
- Verilog-2001 has a more C-like syntax, while VHDL is more Ada-like
- Verilog-2001 can have some confusing concepts for beginners (e.g.
That said, the most important concepts are shared by the two languages, albeit by different names (e.g.
process) and in any case the difficulty in learning an HDL is more related to the concepts behind (such as the concurrency of all processes, the HW conventions etc.) than to the language itself. Considering the differences, if the choice is between Verilog 2001 and VHDL I personally would address any beginner to VHDL.
However, as I said, my suggestion is actually to use neither VHDL nor Verilog-2001 if you have the power to choose. Contrary to what many people assume, SystemVerilog is not a higher-level language useful only for system-level design or verification and has little to share with languages that can be fed into a high-level synthesis tool like SystemC.
Instead, SystemVerilog is a full update of the Verilog language (based on Verilog-2005, see http://en.wikipedia.org/wiki/SystemVerilog) that has a fully synthesizable subset that matches the conciseness of Verilog with higher expressivity than both Verilog-2001 and VHDL, providing in my opinion the best of both worlds.
Examples of very significant constructs/expressions available in SystemVerilog that are not available in Verilog-2001, VHDL or both include:
always_combblocks that help the designer distinguish immediately between blocks implementing different kinds of logic, and - for
always_latch- infer automatically the signals that should go on the sensitivity list (a source of infinite bugs in VHDL and Verilog, especially for beginners!)
logictypes that substitute the confusing
regtypes of Verilog-2001
- packed types that allow easily building multi-dimensional buses (e.g.
logic [N-1:0][M-1:0][P-1:0]), whereas Verilog-2001 supports only two-dimensional buses and VHDL forces the designer to define new types to build similar structures
- high-level constructs such as
struct(similar to VHDL
record) and even higher-level
interfacethat can be used very effectively to model regular structures (such as the ports of a bus)
I tested all this differences "on my skin" while working on a quite complex multicore system for research purposes. It is now supported by many tools, and I know for sure (from using them almost every day) that it is supported by Synopsys tools (both for ASIC and FPGA synthesis flows), Xilinx Vivado (for FPGA synthesis), and simulation tools such as MentorGraphics Modelsim, Cadence NCsim and Synopsys VCS.
To be totally complete, there are two other significant kinds of languages in the toolbox of the hardware designer (though quality of these tools may vary a lot):
- HDL generation languages such as MyHDL (Python-based) and Rocket (Scala-based). The concept here is: you describe your design in a higher level language but still using very HDL-ish concepts (e.g. concurrent blocks, explicit timing) and you then generate conventional HDL (usually Verilog-2001). Honestly I don't find these super useful as the abstraction step from HDLs is small and SystemVerilog provides already many of the higher level concepts, with the advantage that it is directly fed into the synthesis flow with no intermediate steps.
- High-Level Synthesis tools, such as Vivado HLS, LegUp, Calypto Catapult and many many others. These take a very high-level description, often in C, C++ or SystemC and usually untimed, and generate a best-effort implementation in (usually unreadable) Verilog. They are pretty good at generating some objects (for example HW accelerators for functions like convolution, FFTs etc.) but are generally not general-purpose. For example, it's impossible to design a processor core in most HLS tools - the only one I know of is BlueSpec, which is really an hybrid between HLS and HDL generation.
My career for last 13 years was 80% ASIC and 20% FPGA.
VHDL was used for the 1st 3.5 years and the rest were Verilog. I didn't find switching to Verilog difficult, and for location (Silicon Valley) & speed reasons I only code in Verilog today.
Also, I do a lot of Async interfaces, latches and gate level semi custom designs for performance, so VHDL has very little use in my life now. Instead I found SystemVerilog and SystemC much more useful to pick up and use for big engineering projects.
At one stage, tools like Verilator (free! & fast) saved me lots of much needed fund for critical simulations. You don't have this option (yet) for VHDL. And you might never need it if you always swim in a wealthy pool or you don't do >1M gate designs.
Neverless, VHDL is better for beginners before they develop solid HW design principles. My communications with EDA folks here suggest they have done little VHDL developments for past 10 years, and there is a large drive behind HLS today. So there won't be many VHDL tools developers around...
I went for VHDL, mostly because I know C really well and found that trying to write verilog tended to have me writing as if I was targeting a CPU not describing hardware.
Very annoying to write a page of code and realise what you wrote was effectively a sequential program not a hardware design, yea it would synth, but the result was ugly and slow.
VHDL was different enough that I found it much easier to think in terms of logic design and not control flow.
At the end of the day, the language is seldom the hard bit, the skill is in the system design not the typing.
Last year the university that I've studied promoted two open courses for beginners. Both covered the same content but one using VHDL and the other Verilog.
Of course I've asked both professors the differences of VHDL and Verilog. Both couldn't elect the best.
So I've had to do both courses to see which one could be better to me. My first impression was VHDL is more Pascal-like and Verilog is more C-like.
After this I've decided to do only VHDL because, at that time, I was working with Delphi.
But I never worked with FPGA after the course. So this is the best I can help you.
I use VHDL almost entirely. My experience is that VHDL is more common in Europe, Verilog in the US, but VHDL has been making steady progress in the US as well. The strong typing of VHDL doesn't bother me because I use it like an old-fashioned hardware design language as used in small programmable logic, such as PALASM or Altera's AHDL.
The big problem for most people using VHDL is the strong types. They want to make assignments between std_logic_vector (which I think of as a collection of wires in the target) and "int", (which I think of as a number stored in the computer that is compiling the design). The most annoying type conversion I generally run into is between bit_vector (which I think of as a description of a collection of wires in the computer compiling the design) and std_logic_vector. In fact what dragged me over to stackexchange right now was looking for a conversion from char (a character variable stored in the compiling computer) to int.
Back in the day, the most famous conflict between VHDL and Verilog was the design contest arranged by ASIC & EDA magazine. Google "Unexpected Results From A Hardware Design Contest: Verilog Won & VHDL Lost? -- You Be The Judge!", for example: http://www.ee.ed.ac.uk/~gerard/Teach/Verilog/manual/Example/lrgeEx2/cooley.html
The contest was to implement a fairly complicated 9-bit register. It had up/down counting as well as a few other things. The results were that 8 of the 9 Verilog designers had code running after 90 minutes. Zero of the 5 VHDL guys had anything working.
I do not use VHDL like anyone else. The way I use it, the types don't get in my way very often. I'd have implemented the above project the same way I do everything else, entirely in std_logic and std_logic_vector, using (back in the day) the IEEE unsigned library. Instead, I imagine that the VHDL designers did their work with int and got lost in type conversion.
There are two places you can get lost in type conversion: (a) your design, and (b) your test bench. For me, it's just easier to write the test bench (almost) entirely in std_logic so the test bench itself is (almost) synthesizable. By "almost" I mean that I'll define the clock with a delayed assignment that cannot be synthesized. But other than that (and comments), you cannot distinguish my test benches from the synthesized logic.
Anyway, before you decide on a first language to learn (almost everybody has a preference but almost everybody uses both), I would advise looking up that contest and reading the commentary on it.
One of the problems I've observed with VHDL is that since it is a very verbose language, there seems to be a tendency (in the minds of the designers) to believe that it does not require comments. Not true of course, you should write the comments before the code.
I'll weigh on my two cents: I'm a heavy VHDL user myself, but Verilog can certainly get the job done just as well. You can always wrap one in another (albeit with a time and typing cost).
What I've found is that raw VHDL lacks a lot of handy functions. (OR or AND:ing a whole std_logic_vector comes to mind). Thus, building yourself a toolbox of debugged, synthesizable functions goes a long way of increasing your productivity when using VHDL.
Maybe someone could reference a good open-source library that offers all these "good-to-have" functions?
The previous answers pretty much cover the contrasts between the two languages, and this article covers the points pretty well too: http://www.bitweenie.com/listings/verilog-vs-vhdl/
I'd also like to make a couple more points that haven't been mentioned.
I would recommend learning VHDL first for a couple reasons. The strong typing helps some easy beginner's mistakes to be caught by the compiler. I've also heard VHDL is more difficult to pick up after using Verilog first.
Honestly, you can't go wrong with either language; and if you're working in this industry very long, you'll eventually be learning both languages anyway.