I have been working on a program for class which acts as a stopwatch, but I've been having troubles where it doesn't work. (Only one digit, the first that would be shown on the four digit display is ever used, and it is always at 0.) After putting the whole program through a simulation, and seeing it work correctly there, I can only come to the conclusion that the clock is never changing.
As I see it, these are the relevant parts of my code, but feel free to ask for more.
From the top module:
module stopwatch( [...] input clk, [...] );
From the User Constraint File:
## Clock signal NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ #NET "clk" TNM_NET = sys_clk_pin; #TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%;
I have four synthesis warnings.
WARNING:HDLCompiler:413 - "C:\<REDACTED>\counter2bit.v" Line 31: Result of 3-bit expression is truncated to fit in 2-bit target. WARNING:HDLCompiler:462 - "C:\<REDACTED>\clock_divider_true.v" Line 42: if-condition does not match any sensitivity list edge WARNING:HDLCompiler:413 - "C:\<REDACTED>\count_10.v" Line 37: Result of 5-bit expression is truncated to fit in 4-bit target. WARNING:Xst:2677 - Node <decimal_counter/count3/En_next> of sequential type is unconnected in block <stopwatch>.
In counter2bit.v, the truncation is intentional, so long as it's shaving off the MSB; I don't want the third bit anyway. The if condition doesn't match any sensitivity list edge by design; I don't want it updating when that variable does. The truncated 5-bit expression should never happen because it resets when it updates and the value is 4'd9.
count3 is the last block in the counter, and I am not planning on using the En_next to enable another counter.