I am building a 10-channel audio DAC using 10 ES9018 converters and an ultra low phase noise clock (Pulsar) with femtosecond jitter. What would be the best way to distribute the clock's signal to the 10 converters? It is assumed that the clock's board will be mounted directly on the PCB where the 10 converters are soldered. The clock's frequency is 100 MHz.

  • \$\begingroup\$ The device you listed is an ADC not a DAC. \$\endgroup\$ – Andy aka May 6 '15 at 13:46
  • \$\begingroup\$ and I am not sure what jitter and distribution have in common. I'd say that the distribution would affect skew, not jitter. And without knowing your clock frequency little help can be given. \$\endgroup\$ – Vladimir Cravero May 6 '15 at 13:54
  • \$\begingroup\$ My mistake! I'm working on both an ADC and a DAC converter, and I got confused between the two devices. The DAC uses the ES9018. Sorry. \$\endgroup\$ – Ismael Ghalimi May 6 '15 at 14:14
  • \$\begingroup\$ The clock's frequency is 100 MHz. \$\endgroup\$ – Ismael Ghalimi May 6 '15 at 14:17
  • \$\begingroup\$ well 100MHz is borderline, just keep the traces short and nice and you'll be good. \$\endgroup\$ – Vladimir Cravero May 6 '15 at 15:43

For jitter the big thing you want to avoid is noise coupling into the clock lines. Your clock device is single-ended, so that's a strike against you, but you can still consider routing it with shielding. That is, route ground traces next to the clock as much as possible, but avoid vias on the clock line (keeping it all on one layer should be paramount). For skew (also may be important for you), keep the electrical length of the clock lines equal to each converter.

Also, follow these suggestions closely: A Short Course in PCB Layout for High-Speed ADCs


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