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While reading the guide of a chip I'm about to take in use (Intel Edison), I noticed the SoC is specifically not supporting multi-master.

The SoC is always I2C master, it does not support multimaster mode.

However, as far as I know I2C is designed as a multi-master bus. Does this SoC violate the specification or is my understanding of I2C incomplete?

Why is it out-of-the-question for this SoC to be multi-master anyway?

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3 Answers 3

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While multi-master I2C may seem like a superset of single-master I2C, it's perhaps most useful to think of them as though they were separate, since a lone master is allowed to act in ways that would be illegitimate for a bus-sharing master, and such actions can recover easily from failure modes which would be harder to deal with in a bus-sharing system. For an I2C master to coexist with other masters on the same bus, it must include support in hardware and software for such coexistence; this support must, among other things, to include time-out logic to handle the scenario of another master starting communication and then getting reset while SDA and SCK were released (or getting reset while SDA was released and releasing SCK as a consequence of the reset). In that scenario, neither master would be allowed to communicate until both had seen SDA and SCK high for sufficiently long as to conclude that anyone who had held the bus must have "died". Lone-master I2C would not have such an issue, since there will never be any transactions pending it doesn't know about, and time it doesn't want a transaction to be pending it can reset the bus by releasing SCK and SDA (if already asserted), waiting for SCK to go high, and if SDA is low at that time, asserting SCK and restarting the procedure (which may be necessary at most nine times); once SDA and SCK are both high, it can begin the next transaction by asserting SDA.

Because of the differences in design between shared-bus and lone-master firmware, most lone-bus applications would require substantial rework to coexist with other bus masters. Since multi-master hardware would be useless without corresponding firmware, I don't see any need for a device which will be used as a lone master to include the hardware necessary for multi-master arbitration.

BTW, one thing I've not seen supported in hardware, but which would IMHO be useful, would be a means of performing shared-address multi-slave arbitration. The signalling protocol would make it easy for a I2C device to support a "prepare to read device IDs" write address and a "get next device ID" read addresses. The former command would "activate" the read-ID mode of all devices receiving it; the latter would cause any device whose read-ID mode was active to try to output its ID (dropping out if it lost arbitration to any other device); any device which successfully output its ID would deactivate its read-ID mode. Under such a scheme, a master which output a "prepare to read device IDs" and then issued multiple "read device ID" requests would receive back the IDs of all connected devices in a fashion much smoother and easier than that used by one-wire protocol.

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  • \$\begingroup\$ According to the spec, there's no such thing as single-master I2C since I2C is designed to be multi-master capable. The amount of masters present do not change the spec. Your answer seems to assume otherwise, did I misread it? \$\endgroup\$
    – Mast
    May 6, 2015 at 16:55
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    \$\begingroup\$ @Mast: The vast majority of I2C masters that have been built and programmed would grossly malfunction if another device was communicating on their bus when they try to initiate a communication. Perhaps the authors of the spec think the world would be more elegant if I2C master devices were capable of coexisting with other devices on the same bus, but if a board is built that includes a CPU, I2C EEPROM chip, an I2C RTC chip, and no other connection to the bus, the usefulness of the device would be in no way enhanced by adding I2C arbitration logic to the CPU firmware. \$\endgroup\$
    – supercat
    May 6, 2015 at 17:07
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As you say the I2C specification allows for multiple masters connected to the same bus, as well as a ton of other things. This chip happens to realize only a subset of the specification, i.e. it cannot be connected to a bus together with another master.

This should not be a surprise: many devices that adhere to a certain spec usually realize only the necessary subset of that specification. I worked on an Altera board with an FPGA and many devices, one of them was an audio codec that used also I2C. The altera code that talked to the codec probably didn't come anywhere near implementing the full I2C spec, both for multimaster and such and speed. I've seen some prototype chips with an SPI interface that did not support all the speeds that SPI specifies. But you know... It worked.

It was possibly designed so to save money, either in the form of time or silicon area or whatever. There are many use cases where multi master is not needed anyway.

A little addendum: in my opinion you can connect that device to a bus where another master is present but you should carefully test all the possible cases and modify the other master behavior to account for the 'evil' master.

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    \$\begingroup\$ Any time multiple masters are attached to any sort of bus, it will be necessary to have some means of ensuring that they don't stomp each others' communication. If two devices support multi-master I2C, no other arbitration will be necessary. Multi-master I2C is not, however, the only way arbitration may occur. Other simpler schemes might work, e.g. if one master controls the reset line of the other, the latter device may promise to only talk on the I2C bus within 20ms of startup, and the device controlling reset could promise not to talk on the bus within 25ms of releasing rthe reset line. \$\endgroup\$
    – supercat
    May 6, 2015 at 18:54
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According to the I2C Specification Rev 3, found at the bottom of Page 6:

The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it.

So, yes, it does violate the spirit of the I2C specification. The multi-master feature was probably omitted from the chip to save on development cost and/or silicon space.

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