How is byte addressable memory implemented? If the max word size is 8 bytes (64 bits), does the memory always read 8 bytes and then use logic to select the bytes you actually need (1, 2, 4, 8 bytes)? Also, how are the writes implemented?
Generally what happens is you lose the low order address lines and gain byte enable lines. So if you have 4 GB of memory which would require 32 address bits for byte access, you might end up with 30 address bits, 4 byte enables (from the remaining 2 address bits), and 32 data lines for a 32 bit word size or 29 address bits, 8 byte enables, and 64 data lines for a 64 bit word size. Inside the memory, logic will be used to mask which bytes are actually written back during write operations based on which byte enables are selected. Generally the byte enables are only used during write operations, reads will almost always read out the complete word size and whatever is performing the read operation will simply ignore the extra data.
The number of bytes read at a time depends on the data path width. A 64-bit system could read 8 bytes at a time, because 64-bits would show up in parallel. For an 8-bit system, it would read 8 bytes sequentially.
The maximum word size is not determined by the bus width, so if the maximum word is larger than the bus, the bytes are read sequentially. If the bus is larger than the requested data, the requested bytes are returned in the LSBs of the data bus. This is because in 64-bit systems, each byte of memory is addressable, so the LSB of the bus can start with any byte.
The writes work in exactly the opposite direction. From one to how ever many bytes can fit in the data bus are written to a location specified by the address bus.
Except for certain processors, like the 8051, the only time you need to grab more than what you want is to get bits out of a byte. The 8051 has some bit addressable memory, but for anything else you need to grab a whole byte and extract the bits you want.
One thing is the physical memory chips you work with. These always have fixed data width anywhere from 8 to 64 bits, in my experience. As a side note, on DIMM slots often you have multiple chips with their data I/O "parallelized", so that the module, as a black box, delivers 64bits wide bus of data.
Then you have the CPU that wants its data to be transferred. You are right, that with the PC, the entire word is the smallest piece of memory the hardware can access. You are again right, that the CPU/Memory controller then picks the sub-bytes that each individual instruction needs.
I'd also like to relate this issue to alignment, even though the question doesn't mention it.
Many modern architectures expect certain instruction operands to be aligned. This is mainly an issue with SIMD, where you'd normally want 16-byte alignment. The C* language tools often don't make it too easy to achieve.
This comes to your point about the extra logic that's used to re-align the memory block (i.e. cache line) - aligned access is often faster, because this alignment logic is bypassed.
When addressing 64bits wide RAM, a CPU will typically read 8 bytes at once and use multiplexers/selectors to pick bytes.
For writes, there are "byte enable" (or data strobe, or whatever) signals which allow to modify bytes one by one.
This is more complex with EDC memory (72bits or 96bits vs. 64bits) as the error correction code is calculated over all the bits at once and can only correct a limited number of bits spread across the bus. In that case, for modifying only one byte, the CPU need to do a read/modify/write operation.
Which would be very slow.
As most modern CPUs use large write back caches, most writes to RAM are actually copy-backs cycles, so reads are taken from the caches, "real" 8, 16 or 32 bits writes to 64bits DRAM are very rare.