I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets input_IBUF] >
input_IBUF_inst(IBUF.O) is locked to
input_IBUF_BUFG_inst(BUFG.I) is provisionally placed by clockplacer on
For my application I check
rising_edge(input). Kindly provide the solution in this problem.