# How to solve routing issues in Artix7?

I am working with Artix 7 (xc7a15tftg256). When the time of Run Implementation,shows the following error message:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets input_IBUF] >

• input_IBUF_inst (IBUF.O) is locked to IOB_X0Y83
• input_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

For my application I check rising_edge(input). Kindly provide the solution in this problem.

• Sounds as if you're using a non-clock input pin for your clock input. Not all input pins can route directly to the global clock nets in the FPGA. If input is actually a clock signal, and if it's a custom board you're using, I'd say do a redesign and make sure that you use a correct, dedicated clock input. If input is not a clock as such, but just a signal that you want to edge-trigger on, why not just use a "real" clock signal to sample it instead? May 7 '15 at 6:14
• Do you add IOBs during synthesis? Or do you use the IBUF in your design? In that case you should remove it and let the tool decide. May 8 '15 at 8:08

It's recommened to use clock capable pins (CC Pins) for clock inputs. These can be routed to BUFGs.

But the error it in another part of your code. As you wrote you are using

if rising_edge(input) then


You cannot use rising_edge on none clock nets, this promotes them to a clock net, which input isn't.

The correct way is to synchronize the input with 2 D-FF and add an edge detection after that (3rd D-FF, not-gate, and-gate). All FF are driven by your system clock.

input_meta <= input      when rising_edge(Clock);  -- 1st synchronizer D-FF
input_sync <= input_meta when rising_edge(Clock);  -- 2nd synchronizer D-FF
input_d    <= input_sync when rising_edge(Clock);  -- edge detection D-FF (d = delayed)
input_re   <= not input_d and input_sync;          -- edge detection equation (re = rising edge)

process(Clock)
begin
if rising_edge(Clock) then
if (input_re = '1') then
-- do something
end if;
end if;
end process;

• "if risinig_edge(input) then" is oerfectly fine, why do you think it is not correct? Just because it is named INPUT doesn't mean it can not be a clock! May 8 '15 at 8:06
• @FarhadA My answer has 2 parts: 1) regarding CC pin usage for clock inputs and 2) using rising_edge on none clock nets. As you can see, Vivado inserts an IBUF and a BUFG for input, because the OP used rising_edge(input). So either he named a real clock net input (awkward naming for a clock) or the OP used rising_edge on a data signal what is wrong for synthesis (in most cases). Inputting clock signals into a FPGA on none clock capable pins is a design fault. May 8 '15 at 9:24