So I have this design here where I talk via JTAG from a microprocessor to a CPLD.

The JTAG protocol is done via bit-banging of four GPIO pins.

This connection is just very infrequently. It's just for the initial programming of the CPLD and may be used if a bitstream update is needed.

Now the question: What should I do with the JTAG interface during these idle times? Right now I have the interface pins at high-z state, but I could also drive them low or high.

What's the best practice?


2 Answers 2


I would suggest referencing the specksheet for the specific device - they usually have pretty extensive documentation and try to cover most of questions. Here's what I found in my family of devices:

XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 have internal pull-ups on TDI and TMS. CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK. It is recommended to place external pull-up resistors on the JTAG input pins TDI, TMS, and TCK. For a single device, the resistor value of 4.7 kΩ is suggested. This value may be adjusted depending on the number of devices in the JTAG chain or the application. External pull-down termination is not recommended as it would conflict with the internal pull-ups.

  • \$\begingroup\$ The reason why they stress that they do not recommend external pull-downs is that this is what you would infer from the state diagram as the "safe" choice. \$\endgroup\$ May 8, 2015 at 14:52

High Impedance is good and the safest. It is almost the same as disconnecting the IO pins completely.

I say "safest" because it removes any danger of conflicting voltages on the IO pins if the CPLD's pins ever get driven to a specific voltage at any time. You don't want to be driving a pin high at the same time that the CPLD drives it low or you'll be pretty much shorting things out

So stick with Hi-z.


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