So I have this design here where I talk via JTAG from a microprocessor to a CPLD.
The JTAG protocol is done via bit-banging of four GPIO pins.
This connection is just very infrequently. It's just for the initial programming of the CPLD and may be used if a bitstream update is needed.
Now the question: What should I do with the JTAG interface during these idle times? Right now I have the interface pins at high-z state, but I could also drive them low or high.
What's the best practice?