I'm comparing the power consumption of several microcontrollers, FPGAs and an ASIC I've developed, which all perform the same task. For a fair comparison the current consumption must be scaled due to differing manufacturing process technology, especially the process node (micrometer or nanometer, number of metal layers, which metal).

I'm looking for information on the following devices:

  • MSP430F1232
  • MSP430F2232
  • MSP430F5418A
  • PIC16LF727-I/PT
  • ATmega88PA-AU
  • Virtex 4 FX XC4VFX20
  • Zynq XC7Z020CLG484-1

Unfortunately I couldn't find any reliable information in the datasheets and also not with extensive web search. At Microcontrollers Manufacturing Process I found the overview information that Microchip uses 0.25-1.2um, but nothing specific. Further, I found that Virtex 4 FPGAs were manufactured in a 90nm process and Zynq (and the other series 7 FPGAs) in 28nm.

Additionally I'm comparing reconfigurable logic size and amount of configuration data. Therefore I'm searching information on the area of a CLB on the FPGA chip. For example, with a die photograph the size could be estimated.

To compare the amount of configuration data I'm currently using the size of a configuration bitstream file, subtract estimated numbers for IOs, Block RAMs, DCMs, ..., and divide by the number of CLBs. However, this is quite imprecise (also because the bitstream files are not just data but basically specify configuration commands with argument). Therefore I'm interested in the number of configuration bits per CLB (or similar unit) of the above mentioned FPGAs. One thing I've found so far is that the Lattice iCE40 FPGAs use 864 bits per tile (which contains 8 LUTs) (see the reverse engineering project by my colleague at http://www.clifford.at/icestorm/).

Clearly, my question is not related to textbooks or engineering basics but highly specific. I'm hoping that someone in this noble community accidentally came across any of the above information or is himself an employee of the companies and has access to such information or can point me to the proper documents.

Addition 1: Atmel replied that the ATmega88PA is 250nm. The 'A' at the end denotes the "newer" process. Chips without that 'A' are in an older 350nm process. Thanks!

Addition 2: For the following FPGAs I found the process nodes: Virtex: 220nm, Virtex-E: 180nm, Virtex-II: 150nm, Virtex-II Pro: 130nm, Virtex 4: 90nm (300mm copper wafer), 7 Series: 28nm

Addition 3: For Virtex (first version) XAPP151 leads to 864 bits/CLB (which contains 4 4-LUT+D-FFs). For the Virtex 4 I've estimated 2719 Bits/CLB (which contains 8 4-LUT+D-FFs). For the 7 Series I've estimated 4085 Bits/CLB (which contains 8 6-LUTs + 16 D-FFs).

Addition 4: For the Virtex-E I found an estimation of 35462um²/CLB @ 180nm in a paper (however I don't know whether this number is only related to the papers own work). For the 7 Series I estimated 3790um²/CLB @ 28nm. For the iCE65 I found 1750um²/LUT+D-FF.

  • \$\begingroup\$ In a sense, same process comparison is not fair either. The volume or value of energy efficiency for the ASIC might not justify the use of smallest feature size process (FPGAs have somewhat high volume and have a feature regularity that facilitates using redundancy to increase yields). Microcontrollers may be pad limited rather than transistor-count limited and may require a process supporting flash (which would tend to be older). For marketing, the choices available to the customer should be compared; even internal justification should focus on competing solutions and actual tradeoffs. \$\endgroup\$
    – user15426
    May 12, 2015 at 17:34

1 Answer 1


About power consumption. You are comparing microcontroller and programmable logic devices. That's absolutely wrong, because, FPGA consumption depends of a lot of points, as frequency, occupancy, etc. Habitually FPGA software packs provide a tool to estimate the power consumption of a programmable logic design, but to know the real consumption you must measure it directly in a live circuit.

About the configuration data size. This info must be detailed in the datasheet of the FPGA device, because you have to add a flash chip to store this configuration bitstream during power off and you need to know the minimum size of this flash chip.

Best regards

  • \$\begingroup\$ Thanks, but I didn't include a detailed explanation of what I'm really doing to safe space. But it is well thought through. The config data size is only vaguely documented, only the total size (which includes overhead like encoded commands, ...) to select a flash chip. It is however not documented how many bits actually are used per CLB or similar, and my impression is that any information which could fill the gaps in the derivation are carefully hidden. \$\endgroup\$ May 25, 2015 at 18:08
  • \$\begingroup\$ That's right! In fact, the FPGA designer don't need to know these details. \$\endgroup\$ May 27, 2015 at 10:09
  • \$\begingroup\$ But there is a large gap between "you don't actually need the information in your day to day job" and "we refuse to provide the information, why do you dare to ask, you ***" ... \$\endgroup\$ May 28, 2015 at 18:45

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge that you have read and understand our privacy policy and code of conduct.

Not the answer you're looking for? Browse other questions tagged or ask your own question.