2
\$\begingroup\$

This question already has an answer here:

I got to understand what a LUT actually is. The inputs of a logic function acts as drivers for address lines of a memory block (typically a RAM block) and the address lines are decoded to point to a value which is passed on to the output.

Y=A^B

We store the values[0:3]=(0,1,1,0); And based on the input which acts as address,the corresponding output is enabled.

But how is this value actually stored?

I write y<=a xor b;

How is this put into the look up table? And how is this linked with the multiplexers and D-Flipflops?

\$\endgroup\$

marked as duplicate by tcrosley, Scott Seidman, Daniel Grillo, akellyirl, JIm Dearden May 20 '15 at 17:05

This question has been asked before and already has an answer. If those answers do not fully address your question, please ask a new question.

2
\$\begingroup\$

The LUT is loaded with data with the internal configuration logic. Extra logic inside the FPGA (hard logic, not LUTs) reads the configuration bitstream (sof or bit file) from an external flash chip or from the JTAG interface and then stores it into the correct locations inside the FPGA. This includes LUTs, block RAM, clock management components (PLL, DCM, MMCM, etc), and the routing matrix. This configuration routine is triggered after any reset of the entire FPGA (i.e. Xilinx PROGRAM_B or Altera nCONFIG) and can load the bitstream from a number of different sources including JTAG, SPI or parallel flash chips, a microcontroller or microprocessor, another FPGA or CPLD, etc.

The routing matrix is what interconnects the reconfigurable components inside the FPGA. It consists of horizontal and vertical wires of various lengths and interconnecting switches. Closing the correct switches allows signals to be routed around the FPGA between the various components. Dedicated clock distribution networks also exist to distribute high speed, high fanout clock and reset signals.

I would highly recommend looking at an FPGA datasheet to get a feel for how these components are implemented on a commercial FPGA. Both Xilinx and Altera have quite a bit of documentation on the specifics of the routing network and construction of the logic elements.

\$\endgroup\$
  • \$\begingroup\$ I do not get many things here. What is FPGA start up routine? I thought only when we feed the .sof file into the fpga, it will load LUT. I think I am asking about how the code is compiled and how it is actually implemented. Besides I do not get the extra logic part. Could you elaborate on your point? Every point? I am a beginner here \$\endgroup\$ – Muthu Subramanian May 10 '15 at 2:51
  • \$\begingroup\$ There is one more question. Suppose I have logic cells with only four bit LUTs. I write a logic function of four inputs. Only one LUT (or only one logic cell) is enough? and I write a logic function of five variables and how is it implemented in the LUTs? \$\endgroup\$ – Muthu Subramanian May 10 '15 at 2:57
  • \$\begingroup\$ Yes, one LUT is enough for any function with 4 inputs and one output. \$\endgroup\$ – alex.forencich May 10 '15 at 2:58
  • \$\begingroup\$ What about the five inputs? and how is the input routed to a particular logic cell and the output is routed to an I/O pad? I am guessing a routing matrix but I have no idea what it is \$\endgroup\$ – Muthu Subramanian May 10 '15 at 3:05
  • \$\begingroup\$ For 5 inputs it would have to be split up among several LUTs. You will be able to break apart your logic function into pieces small enough to fit on LUTs, though it may require several LUTs to implement the whole thing. \$\endgroup\$ – alex.forencich May 10 '15 at 3:29

Not the answer you're looking for? Browse other questions tagged or ask your own question.