# How to remove this warning in Verilog?

I took a signal sum[8:0] in my code. Further, I need only sum[8] in my code (M.S.B of sum). So I used the statement assign sum[7:0]=0;

It gave me the following WARNING after synthesis:

WARNING:Xst:646 - Signal < sum<7:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.

Should I worry about it or ignore it?

• If you only need the MSB, then yes it is safe to ignore the warning. It's just saying that the lower 8 bits are unused which from what you describe is intentional. – Tom Carpenter May 10 '15 at 13:55

If you know that you don't need the signals, ignore the warning. But why would you declare a 9 bit bus whilst only needing one signal? That's bad practice.

You should definitely worry about it!

This warning means that you're not using signals that you've declared so synthesis -- being the clever thing that it is -- optimised those away. This usually suggests that there's something logically wrong in your implementation and that your output will not be what you intend it to be.

Only ignore warnings that you fully understand.

Finally, don't switch off that warning type as you will not see it when it actually matters!

• Note that the question specifically says the 8 LSBs are intentionally unused. So the warning is safe to ignore. – Tom Carpenter May 10 '15 at 13:56

The warning is correct and you should fix your code. Here is what is happening: your module takes an 8-bit input signal, but you only care about the MSB (that's a legitimate requirement). Therefore, your module has no need for an 8-bit copy of the input. So don't assign the lower 7 bits to zero, it's a useless statement and useless signal.

Instead, your module should just have something like: wire msb = sum[8]. And then use msb in your code.

Then the warning will go away and your module will not contain unused wires.

One way to minimize warnings, but also allow synthesis to trim back the logic cone is shown below. I use this when I am using a stranded bus, but not all of the pins on the bus.

The example comes from :

https://www.veripool.org/projects/verilog-mode/wiki/Faq

// Linting
wire _unused_ok = &{1'b0,
// Put list of unused signals here
1'b0};


To pick off strands from the bus, I use:

wire _unused_ok = &{1'b0,
a_bus[0],
1'b0};