Ok. At the urging of @stevenvh, here's how I'd do it...
The uC that you chose does not have an I2C-Like interface that would normally connect, more or less, directly up to an audio DAC. The ideal solution would be to choose another uC that does support I2C directly, but of course we don't always have that luxury. We could use some of the I/O ports on the uC, but that would take a lot of pins/signals. One thing that could be used is the SPI Master peripheral. So, here's what I propose.
Use a cheap CPLD to interface the SPI port on the uC to the I2C port on a typical audio converter.
Start with an oscillator of appropriate frequency, maybe 24.576 MHz for a 48KHz sample rate. In the CPLD you have a counter that runs off of this clock. The output of the counter is used to generate all of your audio clocks: MCLK, BITCLK, and LRCLK. It is also used to generate one or two control signals.
Another section of the CPLD is an RX shift register. The RX SR can be 16, 24, or even 64 bits long. It gets it's data from the SPI interface on the uC, and transfers it's data to the TX Shift Register at regular intervals. The TX shift register is the same size as the RX shift register, and clocks it's data out to the DAC at the same rate as BITCLK.
The ideal size of the SR's is really a balancing act. You're balancing the size of the CPLD vs. the software overhead vs. the number of bits in your audio. For the moment, lets assume 1 channel of 16 bit audio.
For this example, the SR's are 16 bits long. At the beginning of the sample, the CPLD generates an IRQ to the CPU. The CPU responds by sending the next 16 bit sample over the SPI interface to the RX SR. At the end of the sample, or beginning of the next, the RX SR data is loaded into the TX SR, where it is shifted out to the DAC. So at any given moment there could be two transfers going on at the same time: SPI to RX SR, and TX SR to DAC.
The TX SR is set up so that as data is shifted out, zeros are shifted in. You actually send 64 bits of data to the DAC, but it's OK if the "unused" bits are all zero.
If you want to send 24 bit audio instead of 16 bits then you just lengthen your shift registers to 24 bits. But if you want to go to stereo audio things get a little trickier. I know the OP only cares about mono audio, but I'll include it here for completeness.
You have a choice: You can leave the SR's at 16 or 24 bits, but run the IRQ's twice as fast (and load the TX SR twice as fast). Or you can lengthen the SR's to almost 64 bits. The first option keeps the CPLD small, but doubles the number of IRQ's it has to perform. The second option is reversed.
For a simple single channel of 16 bit audio, you'll need a CPLD with about 48 Flip-Flops: 9 bit counter, two 16-bit SR's, three output clocks, an IRQ, and a couple of extras. This would fit into a Xilinx Coolrunner-II 64-macrocell part which runs around US$1.50 in medium volumes. Altera has some Max V parts that are more Flip-Flop rich that could be cheaper.
As for a proper DAC, there are dozens to choose from. Cirrus Logic, Texas Instruments (Burr Brown) and AKM are the top three that I'd pick from. All of them have an inexpensive stereo DAC that will work fine. The simpler the better. I like the Cirrus Logic CS4334/35/38/39. Digikey has the part for US$3. But the other guys have very similar parts for a similar cost.