I have limited knowledge in hardware design, where i get caught in the following noise issue.

We found out that 1 of a switching regulator we used is interfering our data waveforms as below:

enter image description here

Yellow colour is data waveform and blue colour is waveform form 20V switching regulator.

As seen in the picture, there is a very huge spike that make our data waveform not really smooth.


Switching frequency we set in the regulator (Rt) is 0.6MHz Previously we did a wrong inductance calculation, now we change the inductance value to 20uH to suit our 20V design and it wont help much.

Datasheet for LT3690

SnapShot for PCB layout

Is there any method we can use to filter the spike?

  • \$\begingroup\$ Might help to also provide your pcb layout \$\endgroup\$ – efox29 May 12 '15 at 5:50
  • \$\begingroup\$ I just allow to snapshot for the 20V switching regulation part. Thanks \$\endgroup\$ – WenJuan May 12 '15 at 6:13
  • \$\begingroup\$ IS the spike actually causing a problem? PCB layout would need bottom layer (earth plane layer) too. \$\endgroup\$ – Andy aka May 12 '15 at 7:37
  • \$\begingroup\$ What manufacturers part number is C54? This is a very important capacitor. \$\endgroup\$ – Jon May 12 '15 at 10:20
  • \$\begingroup\$ Is there a ground layer on the pcb? (I'm not seeing it.) \$\endgroup\$ – George Herold May 12 '15 at 12:11

As an immediate band-aid, I would replace C54 with a ceramic X7R or X5R 25V or higher capacitor. Not only is your electrolytic many order in magnitude higher in ESR, it is underrated and will self destruct eventually. Capacitor voltage ratings are never to be exceeded. Ceramic can be used up to close the rated voltage as can film and mica. but all electrolytics should have significant guard band.

Layout comments follow:

As other commenters have mentioned, a four layer stack up with a dedicated ground plane would add substantial noise immunity. If you do so, void out the area under the inductor and run no traces on any layers there. Using a shielded inductor would help as well. The FB and V nodes are high impedance and very noise sensitive. I put those components on the bottom with an intervening ground layer.

I don't want to go on and on about re-laying out the power supply because I am not sure that is an option in the budget and schedule of your project.

One final thought, it looks like ground bounce is the larger problem and induced noise secondary. It would help if you could open up the time base of the scope to just a few periods of data so we can see more.

Best of luck.

  • \$\begingroup\$ Thanks, i will capture the time base waveform later. In the same time i tried change the cap see the result get any better or not and we will try to look on the layout too. \$\endgroup\$ – WenJuan May 14 '15 at 0:23

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