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I am considering using a MOSFET to control the dV/dt rise (slew rate) when power is first applied to a DCDC power supply.

This will hopefully resolve both a precharging issue I am having and the fact the DCDC (LM5008) is breaking if a high dV/dt is applied.

Circuit The circuit is mainly taken from the ON-Semi appnote. With the addition of a zener to protect the gate voltage from getting too large.

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Problem 1. The simulations shows a high current spike (time 50ms), I believe this is cause by the MOSFET gate and C1 charging/floating up to the supplied voltage. Any ideas how I could mitigate this unwanted turn-on of the Mosfet?

Consulted Documents:

  1. The motorola appnote everyone refers to MotorolaAN1542
  2. Similar ON-Semi appnote about a PMOSFET implementation AND9093-D
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First lets start by thinking about how the circuit works: When the circuit is in the off-state, the gate is pulled to the 90V input rail by R4, and C1 is charged to a voltage of 90V, assuming the load capacitor has drained to zero.

When you turn M2 on current begins to flow through R2. This reduces the gate voltage which causes the the MOSFET to begin to turn on as there is now a voltage between the gate and source. As the MOSFET turns on the voltage at the output begins to increase as the load allows it. However, this has the effect of lifting the gate voltage back towards the 90V input rail due to the charge stored in C1 (it is like a bootstrap capacitor). Eventually the charge on C1 drains away through R2 and the MOSFET is able to turn on more and more until it is saturated. This feedback loop is what regulates the dV/dt of the output, independent of the load connected.

The problem with your design is that the time constant of the gate circuit is very low. This means that C1 is discharging very fast, eliminating its ability to moderate the dV/dt. It is still limiting the dV/dt, just to a very high value.

To fix the problem you need to change your bias resistors R2 and R4 (they are far too low anyway). Also note that currently the zener diode is conducting in the bias state which is also preventing the circuit from working properly.

Try using the values R2 = 22k and R4 = 2.7k and then tune C1 until it gives you the slew rate you want.

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    \$\begingroup\$ Your explanation has helped me better understand how this circuit is working but the original question refers to the circuit being energized for the first time. Before 90V is applied to the circuit (T<50) the Gate, Sink, Drain are all at 0V. When 90V is applied (T=50) Sink "immediately" goes to 90V, the gate on the other hand is a bit slower, possible because C1 needs to charge up to the voltage created by the voltage divider R4,R2, M2? This has the effect of the Mosfet turning ON prematurely. \$\endgroup\$ – Alexis May 14 '15 at 12:11
  • \$\begingroup\$ @Alexis, I have encountered this exact problem. Did you ever find a solution? \$\endgroup\$ – jcoffland Jan 2 '17 at 10:23
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I've observed the exact same problem. The spike occurs during the initial connection of the main power supply V2 above, i.e. the 90V one in your case, and is due to the capacitor C1 initially being discharged and connected to the drain which is initially at Gnd level since no current in the load. Hence when power is applied C1 charges from 0V potential difference to a potential difference of V2 (90V here) over some time frame which is dependent on R4 and C1 magnitudes. During this initial charging event the gate has normally doesn't have any initial potential since the NMOS (M2) is off at this stage. However, the addition of C1 pulls the gate voltage to 0V if cap is initially uncharged (which it will typically be). Hence, its potential upon initial power connection is lower than V2 on the source pin. Hence, the PMOS starts up in a fully on state at initial connection causing an inrush current which is dependent on the magnitude of any capacitance based loads connected between to the load side of the PMOS (i.e. drain side) and ground. This behavior somewhat invalidates the whole idea of slew rate control if surges are still seen at initial power-up. Of course this initial surge is stopped when C1 charges to give a gate voltage of V2 turning the switch off. Once it is in this charged state, the PMOS can be switched using logic level at the gate of M2 and everything then works as expected with proper slew rate control. My problem is that inrush currents at initial connection time which can lead to failures.

I've found from computer simulation that moving the Capacitor C1 to a position between the gate and the source instead makes the circuit behave more like one would expect, however larger time constants are needed for similar same slew rates since the governing potential difference is now between V2 and the gate instead of gate and the drain side of PMOS. It also alters the profile of PMOS switch on somewhat but is effective in overcoming the issue that is referred to above. Please also note that a zener protection diodes should also be used to avoid building up of charge at the gate which could destroy the PMOS.

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