I am currently working on an embedded audio processing system for electric guitar. I have constructed two JFET preamps (left and right channels) based on the j201 transistor using the common source self biased topology. I hand matched the two transistors and biased them from scratch and achieved a voltage gain of around x3. When pushed to saturation, the preamps also clip symmetrically, which is a good sign that the biasing point is correct. See design below.

JFET preamp schematic

My problem is that when the outputs from the preamps are connected to the line inputs of the WM8731 codec, almost all gain is attenuated and clipping occurs on the bottom rail. I don't know why this happens. See codec below

Codec connections schematic

I am testing with a signal generator with 10kHz signal at 1.6Vpp with high impedance output.

Codec disconected => pk-pk around 6V, no clipping, clean inverted sine wave

codec disconnected waveform

Codec connected => pk-pk around 2.4V, clipping on bottom end

enter image description here

Again, the only thing I've done is plug in the codec between tests. I'm not sure if this is because of a lack of understanding of JFET characteristics or the codec in question, or even something else entirely. One thought that crossed my mind is that maybe the lower half of the voltage divider created by p2 is being loaded down by something in the codec, but then this would only attenuate the signal and not result in clipping on the bottom rail.

Codec Datasheet

  • \$\begingroup\$ You might want to start going the whole path (plus supply voltages) and check where it starts to differ, without looking at the schematics I would guess the codec thing has a too low input impedance, also is 6Vpp the right level it expects? \$\endgroup\$
    – PlasmaHH
    May 13, 2015 at 12:56
  • \$\begingroup\$ This discrepancy or strange behaviour in the signal is right at the input of the codec. I am measuring the same point in the circuit; output of preamp with or without connection. The codec is not expecting 6V. It expects 3.3V but this was just for demonstrating purposes. I can adjust the pots to get the right voltage range. \$\endgroup\$
    – a_wahab
    May 13, 2015 at 13:33
  • \$\begingroup\$ Just a remark: the symbol for the JFET J201 on the schematic is wrong, that is the symbol of a UJT (Unijunction Transistor), which is a different kind of beast than a JFET. \$\endgroup\$ May 13, 2015 at 14:02

3 Answers 3


From page 3 of the datasheet, it appears the input resistance of the codec is between 15k-30k (nominal, depending on the gain setting). This is of the same order of magnitude as your JFET amplifier's output impedance, so the signal reduction is consistent with what you have observed.

Regarding the clipping, the datasheet states that the input signal must be AC coupled. Your circuit is not doing this as P2 provides a bias current path to ground. This will be affecting the internal bias of the codec and is why it is clipping more on the ground side than the positive.

Putting another coupling capacitor at the output of P2 will fix the offset problem, but if you want the gain to be at all stable, you will have to either reduce the output impedance of your amplifier or add a buffering stage.

However, did you notice that the codec has an internal programmable amplifier? Why don't you just use a JFET configured as a source follower (unity gain buffer) and use the codec chip to scale the signal to match the ADC's dynamic range.


Looking at the datasheet and the maximum voltage ratings on page 6 the datasheet says this: Maximum rating

Here the analogue supply voltage (AVDD) is specified between -0.3V and +3.63V. In the same table the voltage range for the analogue inputs should be between AGND -0.3V and AVDD +0.3V Which means that you have a signal headroom at a maximum of 3.66V which is much lower than your 6 Vpeak-peak.

Further down on page 7 (search for "Line Input to ADC") a typical value of 1 V for an AVDD of 3.3V is specified for the Input Signal Level (0dB).

My guess is that you are feeding the codec with a signal that has a too big voltage swing.


You need to capacitively couple the pot wiper to the input to the CODEC with something like a 1uF capacitor (C2 in the below schematic) so that the proper bias (between AGND and AVDD can be maintained.

The pot pulls the DC level close to AGND (the CODEC input probably looks like two ~20K resistors, one to AGND and one to AVDD).

enter image description here


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