1.It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?
There are a much smaller number of board houses that can do more than 3oz. But if you design your board that way you may be stuck using them forever because there won't be a lot of other options. I would stick with 3oz at most.
A lot of board houses can do 3oz copper. But keep in mind that many board houses don't keep the 3oz copper material in stock. So if you use it you may have to wait an extra week or two for them order the material. This has typically not been too big of a problem in my experience as long as you plan for it in your project schedule.
2.Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?
Its usually the opposite.
If you are going to put any SMD components on the board then its likely your outer layers will still be 1oz and some of the inner layers will be 3oz.
3.If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally
as possible throughout the layers?
It is both preferred and possible to distribute the current equally between the layers, but there is no requirement.
The calculations are a lot easier when every layer is the same.
The best way to do that is to make sure that the current carying shapes on all layers are identical. Also the layers should all be tied together at the source and destination, either by a grid of vias, a plated through hole, or both.
But if you have space on some other layer then by all means use the extra copper, it will only reduce the heat.
4.About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading
the graphs correctly, I need about 11mms of trace width on the top or
I have used the IPC recommendations for trace width without problems. But if you have high current on multiple layers expect the temperature rise to be higher for a given ammount of copper (so use more copper if you have space).
Also its worth estimating the trace resistance. If your cad tool can do this then great, if it can't you can just estimate the number of copper "squares" from one end to the other.
The resistance is typically 0.5m Ohms per square at 1oz or 166u Ohms per square at 3oz.
Using the current and the resistance calculate the trace wattage.
Check that the wattage seems rasonable before proceeding.
Also don't forget wattage generated by connector contacts, crimps, solder joints, etc. Those things all add up when dealing with high current.
5.When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current
source, or placing the vias throughout the high current trace?
It depends on if your source and destination are surface mount or through hole.
If through hole then the plated hole already ties all the layers together so thre may be no need for extra vias.
You want the current to be on as many layers as possible for as much as the route as possible. So for SMD pads there should be vias near the source and destination. Ideally you would put filled vias right in the pad becasue otherwise you would be running all of your current on just one outer layer until you reached the first vias.
Placing any vias away from the source and destination means that some of the current is going to flow on fewer layers for a portion of the route. If you place vias evenly along the whole path its likely that most of the current will go through the first few vias (possibly heating them up a lot) and then less current will go through the vias that are farther away. Therefore you won't get very efficient use out of those vias, and you will need more vias overall with this approach. Since vias take away from routing space it may increas the size of your board overall.