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We need to carry high currents on a PCB (~30Amps sustained), so we are likely to order our PCBs with high copper thickness. So far we've only used 35 microns in our designs, so 'high thickness' for us means, 70 or 105.

We do not know what are the things to watch out for with thickness copper. We'd appreciate any experiences. Since this is a very broad topic, I'll go ahead and ask specific questions:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

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    \$\begingroup\$ I'd like to add: Are there any problems having asymmetrical copper weights? E.g. 35 um on layer 1-4 and 70 um on layer 5 and 6? \$\endgroup\$ – morten Jul 18 '11 at 21:12
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    \$\begingroup\$ This is not high copper density, it's high copper thickness. The density of the copper is pretty much the same, they just vary the thickness. \$\endgroup\$ – Connor Wolf Jul 19 '11 at 0:01
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    \$\begingroup\$ Also, for people who are used to boards with copper thicknesses in ounces (e.g. Americans, Me), 35 Micron = 1 oz, 70 micron is 2 oz, and 105 micron is 3 oz. \$\endgroup\$ – Connor Wolf Jul 19 '11 at 0:09
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    \$\begingroup\$ Density is not just per volume, it may also be per unit area, or for string per unit length. All this is to some extent splitting hairs and numbers should always be joined with units that normally make the context clear. \$\endgroup\$ – russ_hensel Jul 19 '11 at 14:52
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    \$\begingroup\$ Also, it's most definitely not splitting hairs, because I can't imagine many PCB houses would respond in the positive, were you to call them and ask for more dense copper. Density in a PCB context can mean several things, including trace-trace spacing capability, copper thickness, or even substrate thickness. \$\endgroup\$ – Connor Wolf Jul 23 '11 at 4:03
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I'm late to the game, but I'll give it a shot:

1- It appears that for a lot of manufacturing houses, 105 microns is as high as its gets. Is that correct or are higher thickness possible?

Some fab shops can plate up internal layers. The tradeoff is usually larger tolerance in the overall thickness of the board, e.g. 20% instead of 10%, higher cost, and later ship dates.

2- Can the copper in the inner layers be as thick as the copper at the top and bottom of the board?

Yes, though inner layers do not dissipate heat as well as outer layers, and if you're using impedance control, they are more likely to be striplines than microstrips (i.e. using two reference planes instead of one). Striplines are harder to get a target impedance; microstrips on the outer layers can just be plated up until impedance is close enough, but you can't do that with internal layers after the layers are laminated together.

3- If I'm pushing current through several board layers, is it necessary or preferred (or even possible?) to distribute the current as equally as possible throughout the layers?

Yes, it is preferred, but it is also difficult. Usually this is only done with the ground planes, by way of stitching vias and mandating that holes and vias connect to all planes of the same net.

4- About the IPC rules regarding trace widths: Do they hold up in real life? For 30 Amps and a 10 degrees temperature rise, if I'm reading the graphs correctly, I need about 11mms of trace width on the top or bottom layer.

The new IPC standard on current capacity (IPC-2152) holds up well in real life. However, never forget that the standard does not account for nearby traces also generating comparable amounts of heat. Finally, be sure to check voltage drops on your traces as well to make sure they are acceptable.

Also, the standard does not account for increased resistance due to skin effect for high-frequency (e.g. switching power loop) circuits. Skin depth for 1 MHz is about the thickness of 2 oz. (70 µm) copper. 10 MHz is less than 1/2 oz. copper. Both sides of the copper are only used if return currents are flowing in parallel layers on both sides of the layer in question, which is usually not the case. In other words, current prefers the side facing the path of the corresponding return current (usually a ground plane).

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

It's best (and usually easier from a practical point of view) to spread the stitching vias out. Also, there is an important thing to keep in mind: mutual inductance. If you place vias that carry current flowing in the same direction too close to each other, there will be mutual inductance between them, increasing the total inductance of the vias (possibly making a 4x4 grid of vias look like a 2x2 or 1x2 at decoupling capacitor frequencies). The rule of thumb is to keep these vias at least one board thickness from each other (easier) or at least twice the distance between the planes the vias are connecting (more math).

Finally, it is still wise to keep the board's layer stackup symmetric to prevent board warpage. Some fab shops may be willing to go to the extra effort to fight the warpage from an asymmetric stackup, usually by increasing lead times and cost since they have to take a couple tries at it to get it right for your stackup.

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If only fraction of traces need 30A, I would still suggest to solder copper wire on top of the trace. This might even be cheaper to manufacture, as you are not using any 'rare' materials (like 100\$\mu\$ Cu). 2mm\$^2\$ copper wire is dirt cheap and much more robust than thin PCB trace.

Is this current DC? With AC current you might be limited by skin effect.

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  • \$\begingroup\$ Is this a mechanically accepted solution for harsh environments? Would cabled solutions pass vibration and shock tests? \$\endgroup\$ – SomethingBetter Jul 19 '11 at 19:12
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    \$\begingroup\$ Also, I hear about PCB busbars and solid copper blocks that can be mounted on PCBs, but I can't seem to find them in any distributor stock. Maybe I'm not searching right? \$\endgroup\$ – SomethingBetter Jul 19 '11 at 19:14
  • \$\begingroup\$ 'cabled' solution would pass as long as it's soldered to the track, and PCB track is not 0.5mm thin line. I am not sure you can damage it even if you want to ) Haven't heard about copper blocks - but should be expensive. \$\endgroup\$ – BarsMonster Jul 20 '11 at 4:43
  • \$\begingroup\$ @SomethingBetter - Here's one manufacturer (Circuit Components Inc) that claims 64A capacity. Couldn't find a distributor. \$\endgroup\$ – Kevin Vermeer Jul 22 '11 at 14:35
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    \$\begingroup\$ The downside of soldering copper wire to the trace is that then mechanical forces, such as the differing thermal expansion coefficients between copper and fiberglass, or just someone bending the board, can cause the trace to tear away from the board. Copper by itself would be fine, but soldering the whole length counteracts the malleability of copper, making it more rigid and brittle. You'd probably be just as well off having two large plated holes and using the heavy wire between them... so long as skin effect doesn't stop you. \$\endgroup\$ – Mike DeSimone Jul 23 '11 at 4:51
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I think 105\$\mu\$ is the thickest you can get, but I can see no reason why you wouldn't get it on inner layers. A PCB is just a stackup of epoxy, copper and glass fiber. You can play with thickness at will. Thicker inner layers won't be as efficient, of course, since they can't give off their heat to the environment easily; the epoxy is a poor thermal conductor.
We had a design which demanded 16A over several traces, and ended up with 4mm traces top and bottom, and big diameter vias on them from beginning to end. No inner traces, I don't recall copper thickness.

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    \$\begingroup\$ Some design houses have restrictions on inner copper thicknesses, at least in the prototyping stage. The one I use regularly (4PCB) will only do 1 oz in on inner layers, unless you are willing to pay a lot more. \$\endgroup\$ – Connor Wolf Jul 22 '11 at 21:57
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    \$\begingroup\$ If you need thick internal layers, you can pretty much kiss goodbye any cheap fab offers. You'll need to go full custom. \$\endgroup\$ – Mike DeSimone Jul 23 '11 at 4:52
  • \$\begingroup\$ 105 µm is not the thickest you can get, there are some manufactures offering 140, 210, 300 and 400 too. \$\endgroup\$ – Uwe Jul 16 '18 at 15:13
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I think the #1 unexpected gotcha may be: The PCB fab marketing people advertise that they can fab very tight trace/gap widths, and also advertise that they can 35, 71, and 105 um thick copper (commonly called 1, 2, and 3 ounce copper), but they can't do both on the same board. If you want thicker copper, you must space traces further apart than you may be used to on more typical PCBs.

  1. You can always call a PCB fab and ask if they can handle thicker copper. But be sure and ask how much that will cost. Even if they can make thicker copper, you may not want to pay the cost adder.

  2. The copper on the 2 outer layers is always thicker than the inner layers. PCB fabs typically buy "blank" copper-clad boards with 17.5 um or 35 um thickness, etch them and add spacers between them and glue them together, so that's the thickness of every internal layer. Then they drill holes and toss the PCB into the plating bath, which grows a layer of copper in each hole and on the outer layers. The result is that all inner layers have the same thickness, and both outer layers have the same thickness, thicker than the inner layers.

  3. When pushing high currents, you typically want wide, short traces to reduce the resistance and hence the I2R heat generated in those traces. If you have 2 unequal traces on different layers "in parallel", reducing the width of any part of either trace increases the resistance and hence the I2R heat generated, making things worse -- it doesn't matter if you make the board more balanced by reducing the width of the wider trace or more unbalanced by reducing the width of the narrower trace.

5- When connecting multiple layers of high current traces, what's the better practice: Placing an array or grid of vias close to the current source, or placing the vias throughout the high current trace?

I suspect that placing the array close to the current source will give a lower net resistance.

"Are there any problems having asymmetrical copper weights? E.g. 35 um on layer 1-4 and 70 um on layer 5 and 6?"

Early PCB fabs had problems unless the layers were "balanced". My understanding is that modern PCB fabs no longer have those problems, so people could in principle make unbalanced PCB. But most people don't bother -- the standard thin-internal layers, thick-external-layers, with 2 distinct thicknesses, is often adequate for most boards.

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The best source for many of these questions is the PCB vendor that you have selected. Different PCB vendors excel at different types of boards: some are great at high speed, tight tolerances; others are good at high power applications. Most will do just about anything you ask, but there may be a price premium.

You didn't mention whether the high current will be at high voltages. If so then you will have additional creepage/clearance requirements to meet in order to pass product safety requirements.

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