DDR2 data rate and data bus confusion

Question

I've been reading about DDR2 memory for the past few days and have got confused with some of the terms involved. I am mainly confused with discrete memory (single DDR2 memory IC) rather than DIMM module which consists of many such discrete ICs.

I understand that double data rate means the data is clocked on both rising and falling edges of the clock signal. So, for example, if a 16-bit wide bus DDR2 memory IC is interfaced to a microcontroller (with built-in memory controller) at a clock speed of 200MHz (i.e. clock output from the memory controller to DDR2 is 200MHz), how would one calculate the data rate?

As per my understanding, 16-bit bus has 16 data lines, and two data bits are transferred per clock cycle for one data line (for double data rate), meaning effective data rate would be: [No. of data lines (16, bits) x Data bits transferred per data line per clock cycle (2, bits) x Clock rate (200, MHz)] / 8 = 800 MB/s.

(Of course, I am talking of theoretical calculations only.)

Have I got it wrong?

I would really appreciate it if someone could please clear my confusions. Thank you.

Answer 1

You have it right.

This is the "raw" or "peak" transfer rate that you get within a single burst of data. The actual long-term throughput will be somewhat less because of the overhead associated with starting and stopping bursts. However, if the memory controller is smart about interleaving operations on different "banks" within the memory chip, it is possible to get sustained throughput that's very close to the peak value.

With multi-chip memory modules, you simply multiply the numbers for a single chip by the number of chips, since they simply operate in parallel.