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While available in many sizes, the presence of a Type I (pins on the short sides) TSOP is a clear indicator of a flash chip in a typical embedded system.

Is there a technical reason for the manufacturers to use Type I over Type II (pins on the long sides), or it is just that they are making compatible versions of the first available chips?

Why is it different for SDRAM, which generally has pins on the long side?

UPDATE: I clarified that I am asking about the preference of Type I TSOP over Type II TSOP. Added SDRAM reference.

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  • \$\begingroup\$ being compatible (pin numbers and package footprint) is really important. I've never heard of the "type I" you talk about though \$\endgroup\$ – KyranF May 15 '15 at 15:27
  • \$\begingroup\$ @KyranF en.wikipedia.org/wiki/Thin_Small_Outline_Package \$\endgroup\$ – istepaniuk May 15 '15 at 15:31
  • \$\begingroup\$ I don't understand what 'dead giveaway' means, but I believe that a memory chip needs an high surface/pins ratio, thus they place them on the short side only. \$\endgroup\$ – Vladimir Cravero May 15 '15 at 15:35
  • \$\begingroup\$ right, I know what TSOP is but the different "types" is interesting, thanks for the link. As @VladimirCravero said, it's most likely because the silicon chip needs a large amount of space, but the number of pins required is not very high, and physically it makes sense to have the pins on the shorter edges in that case. If you had them on the long edges, you would need to space out the pins far more, and most likely take up more PCB room overall. PCB footprint space is often at a premium! \$\endgroup\$ – KyranF May 15 '15 at 20:27
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Having pins on two edges makes it possible for a manufacturer to form a variety of sizes of memory chip by combining a "left side" (common to all sizes), one or more repetitions of a "middle" section (common to all, but for the number of repetitions), and a "right side" (common to all sizes). The length of the connection sides of the chips will remain the same for all sizes of chip; in the smallest chips, the non-connection edges will likely be shorter than the connection edges, and in the largest ones, the non-connection edges will likely be longer. If one figures that the dies for larger flash chips are likely to have the pins on the short sides, it makes sense to lay out the packages that way also (smaller chips could fit in packages either way, but if a large chip has connections on the short side, connecting it to a package with pins on the long side could be awkward).

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    \$\begingroup\$ I clarified my question. + Why doesn't this long-side awkwardness affect the package of choice of SDRAM then? Are the dies that different? \$\endgroup\$ – istepaniuk May 18 '15 at 23:43
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Design of integrated circuit packages is all about:

1) Size /form factor

2) Handling the number of pins required (which is why ball grid and pin grid array packages were developed)

3) Keeping lead inductance down to a minimum for high frequency/speed performance (which is why ball grid arrays and surface mount devices exist)

TSOP - thin small outline package. Thin because that's what consumers/manufacturers want to make things as thin as possible

And placing all the pins/leads on the shortest side means that the lead inductance can be kept to a minimum. Inside is a lead frame which holds the die, if you use the longest side of the TSOP package some leads inside the TSOP package to the die are going to be substantially longer than others which could reduce the upper limit on performance of the memory chip.

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  • \$\begingroup\$ Though with more variation from center to edge, Type II TSOP (pins on the long side) has shorter, not longer leads than Type I. Your other points remain true for every package, but you do not address why this particular choice for flash chips. \$\endgroup\$ – istepaniuk May 18 '15 at 23:45

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