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When designing circuits using various components such as IC's a lot of the time the data sheets give you an example schematic where they will usually give you some values for decoupling Capacitors. I usually see a 0.1 uF cap in parallel with a 10 uF cap on the supply rail. Sometimes I see other variants where they have several 0.1 uF caps in parallel. How are they determining these values?

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    \$\begingroup\$ I'm pretty sure you mean "decoupling capacitors". Coupling capacitors are used to couple a signal from one stage to another, usually on the input of AC-coupled amplifiers. \$\endgroup\$ – WhatRoughBeast May 16 '15 at 0:39
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Short answer:

They start with the standard (0.1 uF in parallel with 10 uF) and if they still have supply bounce issues they start experimenting until it works.

Longer answer:

The exact value of the decoupling capacitor isn't critical, typically, unless you already know something about the frequency components of the noise you expect to see.

Typically, the smaller the capacitor, the higher the self-resonance frequency (the frequency at which the device stops acting like a capacitor and starts acting like an inductor due to internal phase shift). That is why datasheets typically show multiple devices in parallel. The 10 uF is to bypass lower frequencies while the smaller capacitor is effective at higher frequencies (and less effective at lower frequencies because it is smaller).

When you bringing up a new chip on a test board, the product engineers where I work typically use a standard decoupling of 0.1 uF in parallel with 10 uF as you say. If that is good enough, then great, they're done. If there are still supply bounce issues then they will experiment (analysis and simulation is not super helpful here) until they get the noise under control. They do this by adding smaller caps very close to the chip or sometimes, like you saw, parallel 0.1 uF caps. This works because different 0.1 uF caps are different distances from the chip so they interact with the supply bounce in different ways (and at different frequencies).

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  • \$\begingroup\$ Thanks, your answer was helpful and it shed light on the whole process involved in Decoupling. \$\endgroup\$ – Aaru May 16 '15 at 0:46
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    \$\begingroup\$ Paralleling 4 or 5 0.1-uF caps also puts their ESR and ESL parasitics in parallel, making the combination more effective than (for example) a single 0.47-uF cap. \$\endgroup\$ – The Photon May 16 '15 at 0:57
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    \$\begingroup\$ Good answer. There are further dimensions to this, such as : once the circuit is basically working, it may fail testing to meet EMC emissions regulations. If such emissions can be traced to the power supply, further decoupling may be required close to the device generating the noise. This is obviously dependent on the board layout, so not always possible to predict in advance. \$\endgroup\$ – Brian Drummond May 16 '15 at 9:13
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Different values of capacitors optimally filter out different frequencies. I always found this article on filtering and decoupling capacitors useful, it gives a lot of information on the principle behind decoupling capacitors and the differences between certain values.

http://www.ti.com/lit/an/scaa048/scaa048.pdf

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First find resonance (\$ f \$) with the C and your equivalent L for the circuit;

(For DC use, you would be finding as close to the frequency of oscillations on the supply, this is MEASURED, NOT CALCULATED)

$$ f = {1 \over 2\pi\sqrt{LC} } $$

Then use that frequency, e.g. 100kHz, find the bandwidth of the frequencies (\$ \Delta f \$) you are filtering for use, e.g. 10%, so 90kHz - 110kHz.

(For DC use, you want to cover the entire width of frequencies you see on your scope, i.e. the fastest disturbance is 110kHz, the slowest is 90kHz)

$$ \Delta f = {f \over Q} $$

Q is what we're looking to manipulate, which you can get with;

$$ Q = {1 \over R} \times {\sqrt L \over C} $$

So there's an inverse relationship of Q to C. For less bandwidth (i.e. more 'quality (Q)'), have less C. But we want more bandwidth, so we add more C.

R is probably going to be dominant, you can't really get a \$ \sqrt L \$ measurement, so screw \$ \sqrt L \$, solve for Q with regard to CR;

$$ Q = {1 \over C R} $$

Plug that back into our other thing and you get an approximation that you can experiment with;

$$ \Delta f = {f \over {1 \over C R}} $$

In short;

$$ \Delta f = f C R $$

You can measure R, you can measure f, you know you want \$ \Delta f \$ to be \$ f \$+ 10%


Therefore, for an inaccurate approximation for DC;

$$ C = { \Delta f \over f R} $$


And for an ideal approximation at \$ f \$;

$$ C = { \Delta f \times \sqrt L \over f \times R \times X_L X_C} $$

You just put the \$ \sqrt L \$ back in, and take into account the impedance at a certain frequency.

For the ideal C over a range of frequencies \$ X_L \$ and \$ X_C \$ change inversely over \$ f \$ as it goes up such that \$ X_L \rightarrow \infty \$ and \$ X_C \rightarrow 0 \$. They stabilize at resonance, and we find ourselves back at

$$ f = {1 \over 2\pi\sqrt{LC} } $$

Assuming you can find an ideal C. But all Cs have a maximum 'range', i.e. electrolytics are not valid at high frequencies, ceramics are. This assumes you know that you need either high or low frequency protection, and then you can filter. To find out which one you need, just measure \$ f \$ and if it's higher than 100kHz, don't use an electrolytic bucket thing.

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Find the maximum frequency of the decoupling from the fastest rise time / other means..... Altera.com has so many articles regarding power supply decoupling.

Find the transient impedance of the power supply = deltaV ( Tolerance of rail)/Delta Current(transient current). This should be met over the complete frequency range. Most of the board decoupling effective only up to 80 MHz. After that mounting inductance effect comes....after this limit only package decoupling caps will help. Most of the times capacitor value not much matter only mounting inductance and it's ESL matters. In this 80Mhz, you have to design decoupling n/w. Mostly divide into 3 sections(Always select the smallest size or lower ESL caps with larger capacitance). first Bulk capacitors (>47uF---> exact values are approximate) like 100uf,330uf..generally placement of these caps won't much matter. 2nd mid range cap's (>1uf and <47uf --> exact values are approximate) 3rd range will be smaller caps -0.01,0.1uf's --> placement critical.if not placed at proper places no effect.

PDN N/W simple simulation model

free simulators should help like LTSpice 4,spicap etc. get recommendations from manufacturers.

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