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I have a cache memory simulator with this cache memory shown.

enter image description here

The cache size is 64 bytes and the block size is 8 bytes. What is the decomposition into fields? If block size is 8 bytes, then log(2^3)=3 bits are for block offset to point out a byte within a block. For 64 bytes with 8 bytes per row, it will have 8 rows and hence 3 bits for index bits, one bit is the dirty bit that should flag for dirty data and the rest = 25 bits are for the tag. Is this interpretation correct? Then what is meant by the 31..6..3..2..0 and the white and grey color of the incoming address?

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    \$\begingroup\$ The cache apparently does not operate on bytes but on 32-bit words; i.e. 2 words per line. Bits 31 through 6 (25 bits) are used for the tag, bits 5 through 3 (3 bits) address the cache line, and bit 2 selects one of the two words in a line. Bits 1 and 0 would identify the byte inside a word, but this does not concern the word-based cache. \$\endgroup\$ – JimmyB May 16 '15 at 22:51
  • \$\begingroup\$ @HannoBinder Thank you for the comment. I will accept your comment as an asnwer if you add it as an answer. \$\endgroup\$ – Niklas Rosencrantz May 17 '15 at 6:08
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    \$\begingroup\$ done :) {... padding here ...} \$\endgroup\$ – JimmyB May 18 '15 at 8:35
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This cache apparently does not operate on bytes but on 32-bit words; i.e. 2 words per line.

The numbers above the address are meant to designate the index of bits in the 32-bit address. Read from right to left they indicate that one field starts at bit 0, the next field starts at bit 2, then comes one starting at bit 3, and the last field starts at bit 6 and extends up to bit 31, inclusive.

These numbers indicate that bits 31 through 6 (25 bits) are used for the tag, bits 5 through 3 (3 bits) address the cache line, and bit 2 selects one of the two words in a line.

Bits 1 and 0 would identify the byte inside a word, but this does not concern the word-based cache; hence they are not used by the cache logic and that's why the author chose to grey-out their value.

(Note that the values of the fields in the address are to be read as "right-aligned", i.e. the tag is the upper 25 bits of the address where the lowest bit (bit 6) represents the LSB (bit 0) of the tag's value. In other words, the upper 25 bits are shifted to the right by 6 bits to obtain the actual tag value. The same applies to the other fields.)

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