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I'm back to diagnosing power supply failures, in an LLC resonant SMPS based on the L6598, from a 400 V PFC supply with ostensibly 400 W output. I'm new to SMPS, and learning this all as I go, and the manufacturers don't know what they're doing, either; they just copied the design and modified it for more bigger power. The circuit is basically like Figure 3 in AN-9425, but the OPOUT overcurrent detection triggers EN1 (latched) instead of EN2 (soft-start reset).

The failures happen during overload, when the supply is making audible screaming noises and the output voltage has dropped (because it's switching below the resonant frequency, right?) Sometimes it can withstand a prolonged overload (without triggering EN1), sometimes it can't. Sudden transient overloads are usually what kill it. Not sure if it's a progressive damage thing that eventually results in failure or a random spike that exceeds a limit. Theoretically, it should handle overloads by shutting off momentarily or otherwise protecting itself, not by exploding.

Theoretically, I could change the overcurrent protection so that it detects when it's being overloaded and triggers the soft-start EN2 protection mode, shifting the frequency up high to drop the output voltage instead of dropping below the resonant point. I tried modifying the circuit to match the app notes so OPOUT drives EN2, but that just made it blow up even more quickly when I overloaded it.

The L6598 controller IC always fails, the STW20NM60 MOSFETs fail sometimes (high side short across all pins, low side short from D to S), so I think the IC is failing first and taking the MOSFETs with it? The MOSFETs don't have built-in gate protection, so I added Zeners externally and they haven't failed since (yet). New ICs measure open circuit from any pin to any other, but after I remove a failed IC from circuit, some of the high pins will have kΩ between them (12 Vsupply, 14 Vout, 15 high side driver, 16 bootstrap cap).

Today I was manually triggering the EN2 pin, which worked fine at low loads, changing to a high switching frequency and output voltage dropping. At about 200 W out, it worked fine when I enabled EN2, but when I let go of EN2 it would shut down (overcurrent protection triggering EN1 is the only way I know of) and then another time failed. After it failed, the low side driver would still switch at fmin (no output voltage to drive the feedback loop), but the high side driver just had spikes and weird shapes on it, not a square wave. The MOSFETs measure normally with an ohmmeter and didn't explode. So some kind of spike is killing the high side section of the IC and I need to prevent that.

I certainly don't see any pins going higher than the 618 V absolute max rating. I do see tiny spikes going down to -3 V before the rising edge on Vout and VHVG, which are rated for -1 V. I don't know if that really matters. I'm not sure about the ratings for Vout or VHVG, or how I would even measure those (differential probe?), or what conditions would cause them to go beyond the stated limits. They seem to track each other, as would be expected if the high side driver is floating relative to Vout.

What am I missing?

Update:

There are huge bursts of oscillation(?) ±25 V on the gate driver while overloading, 100s of ns after the rising or falling edges, which coincide with the audible noise. These could easily break through the gates and destroy the FETs, so they are the prime suspect. They originally had ferrite beads on all the FET pins, which did not prevent this, nor does removing them. I've added Zener protection to the gates, though, which should prevent them from being destructive, but I'd like the eliminate the bursts themselves first.

enter image description here

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    \$\begingroup\$ Some SMPS beginners project :-) !!! The question is - where is the energy coming from that destroys the IC? If the FETS are destroyed, anything can happen. If the FETs are not destroyed, what is the energy path? \$\endgroup\$ – Russell McMahon Jul 20 '11 at 3:14
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    \$\begingroup\$ Alas many possibles - eg Vout floating at up to V+in!. Where did you get the main transformer from? Is it competently done. May there be eg leakage reactance coupling to Vs? I assume EN1 shutdown is working OK? Datasheet shows it as a supply overvoltage shutdown.How does L1 behave under overload current? Saturating? Data sheet: st.com/stonline/products/literature/an/9425.pdf#page=5. \$\endgroup\$ – Russell McMahon Jul 20 '11 at 3:29
  • \$\begingroup\$ @Russell: The main transformer is custom and was getting excessively hot, so we had them use a bigger one. EN1 shutdown seems to work fine. L1 is integrated as leakage into the transformer. I don't know if it's saturating. \$\endgroup\$ – endolith Jul 20 '11 at 4:01
  • \$\begingroup\$ Define 'excessively hot'. Some magnetics are rated to go well over 100C without ill effects. \$\endgroup\$ – Adam Lawrence Jul 20 '11 at 20:29
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    \$\begingroup\$ @Madmanguruman: melting, smoking, failing, etc. :) \$\endgroup\$ – endolith Jul 20 '11 at 20:31
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I have a suspicion that your problem might have to do with the bootstrap circuit, as detailed in section 5.3 of the data sheet. Some evidence leads to this conclusion:

  • You are likeley using larger MOSFETs than in the original design (because your overall power is greater), thus you are dealing with a higher gate charge, resulting in a higher current that must be delivered by the integrated bootstrap circuit. It could be that the bootstrap circuit dissipates more power than it was designed for and fails, sometimes resulting in a bad output driver for the high side MOSFET, sometimes taking the MOSFET with it. Adding an external, fast and high-voltage bootstrap diode might help. Note that the calculation in Eq. 9 of sect. 5.3 uses the typical on-resistance of the integrated bootstrap circuit. It's a better idea to use the max. value from table 4 which is twice as high.

  • Once the circuit goes into overload, you say that the frequency drops. During these prolonged on-times, the voltage across the external bootstrap capacitor might become too low to keep the high side MOSFET saturated, causing it to have a higher on-resistance, excessive losses and thermal overstress. However, in this case, it would be the high-side MOSFET that fails first. Check the voltage across the bootstrap capacitor. A bigger capacitor might help, but this will likely put more stress on the integrated bootstrap driver or the external diode that might be necessary anyway.

Another possibility could be that you are exceeding the maximum slew rates for the high-side driver. This might cause it to do weird things.

Concerning the negative spikes, an external protective clamping diode at each driver's output might help (K=Vout,HS; A=GND,LS and K=Vout,HS; A=GND,HS). Something as simple as a 1N4148 might be enough.

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  • \$\begingroup\$ But wouldn't the gate drive current be constant regardless of loading? Boot cap is 100 nF and it uses STW20NM60 FETs with 1450 pF input capacitance and a 22 ohm gate resistor. \$\endgroup\$ – endolith Jul 20 '11 at 13:44
  • \$\begingroup\$ You mentioned that depending on the load, the frequency varies. The gate drive current is proportional to the switching frequency: The more often you charge Qg, the more current needs to be provided. A high switching frequency may result in a low voltage for the high side driver. Also, a low frequency may result in a low voltage towards the end of each on-time for the upper MOSFET. Also, I have edited the answer for another possible mode of failure. \$\endgroup\$ – zebonaut Jul 20 '11 at 20:14
  • \$\begingroup\$ Ah, yes. The frequency of LLC converters decreases with load, though, approaching the resonant peak (50ish kHz), so the gate current would be highest with no load (80 kHz) or during the soft-start reset (330 kHz), and I don't see failures in either of those cases. The drop in gate drive for longer turn-on times seems plausible, I'll measure that, but I've seen the IC fail several times without the MOSFETs failing. \$\endgroup\$ – endolith Jul 20 '11 at 20:39
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I think that the burst is the coil ringing at 55 Mhz self resonance frequency. The workaround is to put 2x 470pF caps in parallel to power transistors, to convert coil energy of resonator to lesser peak voltages during ringing oscillations. (This solution I see in similar datasheets from same manufacturer).

Independent test is to calculate energy of coil for given current and inductance and convert to voltage on parasitic capacitance (maintaining the same energy) and see if it exceeds the max voltage of IC.

V=SQRT(E*2/C), where E=L*I*I/2, if V > max then fail

Why the burst is delayed by 366 ns is a mystery. Cable to load, should be about 50 meters to reflect back the transient to make it that late.

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  • \$\begingroup\$ Resonance of what coil? The resonance of the LLC network is roughly 50 kHz. \$\endgroup\$ – endolith Jul 27 '11 at 1:06
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    \$\begingroup\$ The L coil of LC tank. There is only one. Self resonance frequency is that high because parasitic capacitance of coil is in pF range. The nF caps are disconnected by design when oveload happens. \$\endgroup\$ – user924 Jul 27 '11 at 12:49
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    \$\begingroup\$ nxp.com/documents/application_note/AN99011.pdf page 19 \$\endgroup\$ – user924 Jul 27 '11 at 14:48
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    \$\begingroup\$ Yes, high dV/dt will make everything a thryristor. But that is another theory of operation in fail mode. My understanding that fail mode is lossless ringing of grounded disconnected coil when high side of coil is floating and dissipating on nearly infinite impedance. Like a spark coil in the car, or CFL curcuit \$\endgroup\$ – user924 Jul 27 '11 at 16:44
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    \$\begingroup\$ Two capacitors can be replaced with snubber (25 Ohm + 1..10nF) in parallel to coil. img522.imageshack.us/img522/7105/54498575.jpg, Other kind of snubbers for IGBT in SMPS can be pdf1.alldatasheet.com/datasheet-pdf/view/240810/CDE/… where snubber is a module with diode, cap and resistor, one module per IGBT. Latter is more expensive, but more power efficient. All will help to remove ringing burst of residual energy during overload. \$\endgroup\$ – user924 Jul 28 '11 at 16:06
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These sorts of failure modes are always fun to debug. Here are some thoughts:

It's very unlikely that the IC dies first - it's much more likely that the MOSFET is being poorly controlled, fails, and the HV comes through the device into the control IC and is killed. (Either that or the converter is getting into ZCS mode and the MOSFET is under heavy stress - either way, dead MOSFET = dead controller; the opposite often does not hold true)

A well-designed power supply should never scream when overloaded. Screaming usually implies extremely high, rapidly changing current passing through a magnetic component which tends to support the theory that proper control is being lost and the converter is going bezerk before self-immolating.

The common thread in what you've described is that at a certain point when overloaded, the power supply blows up. I'd strongly consider setting the peak current limit lower so that the power supply never 'screams' (voltage divider on OPIN+) and see if this helps.

If not, there's a fundamental issue with the implemented protection mode (nothing to do with the overload itself).

You were able to blow it both in heavy overload (> 400W) and at lighter load by playing with the enable circuit. This rules out the PFC stage dropping out as a cause, which helps. This also rules out transformer saturation. It's starting to appear that the supply simply doesn't like to be inhibited or otherwise constrained. Perhaps the range of frequencies is too broad?

Measuring tiny spikes on the high-side is notoriously difficult without a good scope and a high-bandwidth differential probe.

The driver circuitry in the IC is only capable of 250mA (both high-side and low-side). To me, that's an awfully low amount of current for high-voltage MOSFET drive (high-voltage MOSFETs tend to have large gate charge requirements) - I suspect that turn-ons are going to be slow. What MOSFETs are they using?

The theory that Vout is floating up to Vin is unlikely, unless everything on the Vout rail is also blowing up when the primary goes.

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  • \$\begingroup\$ Well, maybe 4 out of 6 times it's failed, the MOSFETs didn't fail, which is why I think it's the IC that goes first. \$\endgroup\$ – endolith Jul 20 '11 at 21:38
  • \$\begingroup\$ An alternate damage path (in HV applications) is a path from the drain of the MOSFET to the gate (through internal parasitic capacitances), through the drive resistor and onto the IC, which can be enough to destroy the driver. When the FETs failed, were the gate resistors also damaged? \$\endgroup\$ – Adam Lawrence Jul 20 '11 at 21:40
  • \$\begingroup\$ Both times the FETs failed, the high side had all 3 pins shorted and the low side was shorted from D to S. In one case, neither gate resistors failed, but there's also a 1N4148 diode in parallel like AN1673, and it shorted on the low side. But the low-side gate did not short. In the other case, the low-side gate resistor burnt (but so did everything else, including the 10K gate-to-ground) \$\endgroup\$ – endolith Jul 20 '11 at 22:02
  • \$\begingroup\$ @endolith It's starting to appear that you're going to have to sacrifice a unit to see what's going on. If you have a storage scope, monitor the low-side gate drive and do what you need to do to make the unit blow. You'll be able to see things like frequency change, erratic control, etc. - if the bottom gate drive appears to be perfect up to the point of explosion, the fault may indeed be in the high-side (be it drive, bootstrapping or HV damage through parasitic coupling.) \$\endgroup\$ – Adam Lawrence Jul 20 '11 at 22:15
  • \$\begingroup\$ @endolith To me, if the IC fails, switching should simply cease. There shouldn't be a destructive mechanism - same as the OC latch-off. Switching stops and the supply should settle to a safe, quiescent state. I'm still somewhat skeptical that the IC is dying first. If you can find a 12V TVS, put one across the gate-source of each of the STW20NM60s and see what happens. The Qg for those FETs is actually quite low (54nC) so the weak drive may not actually be as much of an issue as I suspected. \$\endgroup\$ – Adam Lawrence Jul 20 '11 at 22:21

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