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I am new in this field. I have a problem with conversion of std logic input into real values. I have been using to_float function but it always showed error. When I used package float_generic_pkg, it showed error:

Cannot find in library .

I also tried creating new library ieee_proposed but still it showed error.

I tried using IEEE.numeric_std.all, too.

Again it gave error <to_real> not declared.

Do I need to use some other library package?

I am using ISE Design Suite 14.7. One thing more: its for synthsis too. Please help me.

Here is the code :

library ieee;
use ieee.std_logic_1164.all; 
use ieee.float_pkg.all; 
use ieee.float_generic_pkg.all; 

entity dafsm is 
port (x : in std_logic_vector (1 downto 0); 
      y : out std_logic_vector (1 downto 0)); 
end dafsm; 

architecture fpga of dafsm is 
   signal r,s : real range 0.0 to 15.0; 
begin 
   r <= to_float(x);
   s <= r * 0.5; 
   y <= to_slv(s); 
end fpga;

The error messages:

Line 4: Cannot find <float_pkg> in library <ieee>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
Line 5: Cannot find <float_generic_pkg> in library <ieee>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file.
Line 12: <real> is not declared.
Line 14: <r> is not declared.
Line 15: <s> is not declared.
Line 16: <y> is not declared.

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  • 1
    \$\begingroup\$ to_float is correct, either in VHDL-2008 from ieee.float_pkg or using ieee_proposed. So post the exact error message from this version and a minimal example that produces the problem. \$\endgroup\$ – Brian Drummond May 18 '15 at 9:36
  • \$\begingroup\$ Thanx for your help, Sir. Here is the code : library ieee; use ieee.std_logic_1164.all; use ieee.float_pkg.all; use ieee.float_generic_pkg.all; entity dafsm is port (x : in std_logic_vector (1 downto 0); y : out std_logic_vector (1 downto 0)); end dafsm; architecture fpga of dafsm is signal r,s : real range 0.0 to 15.0; begin r <= to_float(x); s <= r * 0.5; y <= to_slv(s); end fpga; \$\endgroup\$ – aman2392 May 18 '15 at 15:47
  • \$\begingroup\$ Line 4: Cannot find <float_pkg> in library <ieee>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. Line 5: Cannot find <float_generic_pkg> in library <ieee>. Please ensure that the library was compiled, and that a library and a use clause are present in the VHDL file. Line 12: <real> is not declared. Line 14: <r> is not declared. Line 15: <s> is not declared. Line 16: <y> is not declared. Please help me Sir \$\endgroup\$ – aman2392 May 18 '15 at 15:56
  • \$\begingroup\$ Are you setting the tools to use VHDL-2008? \$\endgroup\$ – Brian Drummond May 18 '15 at 16:41
  • 1
    \$\begingroup\$ There's no VHDL-2008 support in ISE. forums.xilinx.com/t5/Synthesis/VHDL-2008-support-in-ISE-14-7/… \$\endgroup\$ – mng May 18 '15 at 18:39
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I made some changes to your code. The changes will be explained below.

library ieee;
use ieee.std_logic_1164.all; 
library ieee_proposed;
use ieee_proposed.float_pkg.all; 


entity dafsm is 
    port (
        x:      in  std_logic_vector (31 downto 0) := x"0000002A"; 
        y:      out std_logic_vector (31 downto 0)
    ); 
end dafsm; 

architecture fpga of dafsm is 
    function to_string(inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        -- report "image_str = " & image_str;
        return image_str;
end;
    signal r,s : real range  0.0 to 15.0;  
begin 
    r <= to_real(to_float(x));
    s <= r * 0.5; 
    y <= to_slv(to_float(s));
monitor: 
    process(s)
    begin
        report "y = " & to_string(to_slv(to_float(s)));
    end process;
end architecture fpga;

This analyzed, elaborated and simulated.

The changes:

  • I modified the context clause, including a library reference for ieee_proposed, removed anything not needed.
  • `x` and `y` were too short to use. I increased them to length 32 as a first attempt. I don't recall the minimum length off the top of my head, you can find that out by reading the documentation on the above web site or reading the package source code. It can be shorter, I knew 32 would work.
  • I added a default value for `x` (the hex equivalent of 42 decimal). This is so I could your design without writing a testbench.
  • I added a function to_string[std_logic_vector return string], this was done on ghdl, which isn't IEEE Std 1076-2008 compliant, and the function wasn't available. I wrote the function to comply with the standard, section 5.7 String representations (I had this lying around). It's only needed here to verify that the input 42 times 0.5 is 21.
  • The package float_pkg is obtained from the VHDL-2008 Support Library web page, a careful reading provides a download link for the -1993 compatible version.
  • There are modifications to your concurrent signal assignments. There are no real to/from std_logic_vector conversion routines. everything is piped through the new type float.
  • I added a monitor to tell us what the result is.

You carefully scrubbed any vendor identifying information from your error messages and I don't have their implementations any way, I used ghdl.

I first compiled the sources in a directory named ieee_proposed to create a library ieee_proposed:

ghdl -a --work=IEEE_PROPOSED standard_additions_c.vhdl
ghdl -a --work=IEEE_PROPOSED standard_textio_additions_c.vhdl
ghdl -a --work=IEEE_PROPOSED std_logic_1164_additions.vhdl
ghdl -a --work=IEEE_PROPOSED numeric_std_additions.vhdl
ghdl -a --work=IEEE_PROPOSED numeric_std_unsigned_c.vhdl
ghdl -a --work=IEEE_PROPOSED fixed_float_types_c.vhdl
ghdl -a --work=IEEE_PROPOSED fixed_pkg_c.vhdl
ghdl -a --work=IEEE_PROPOSED float_pkg_c.vhdl

We don't need all these to demonstrate your code, but there your are.

Then analyzed, elaborated and simulated your code:

ghdl -a -P./ieee_proposed dafsm.vhdl
ghdl -e -P./ieee_proposed dafsm
ghdl -r dafsm
dafsm.vhdl:33:9:@0ms:(report note): y = 00000000000000000000000000000000
dafsm.vhdl:33:9:@0ms:(report note): y = 00000000000000000000000000010101

There are two outputs because there is an initialization event on s before s is assigned r * 0.5. Note I made the monitor process sensitive to s because y is an output and can't appear in a process sensitivity list. I recreated the the value y will have assigned.

The second is the result, 15 in hex is 21 decimal.

The -P./ieee_proposed tells ghdl to look in the current directory for a subdirectory library ieee_proposed (the name of the directory is the same as the library). I could have placed it in ghdl's library search path, it seemed unnecessary for this demonstration.

Other tools usage may vary.

David Bishop assures us this should be synthesis eligible. I haven't tried myself.

Please avail yourself of the documentation on the above web page.

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  • \$\begingroup\$ Thanx Sir for your great help :) \$\endgroup\$ – aman2392 May 19 '15 at 8:05

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