# Problem with calculating propagation delay

I need to calculate the propagation delay for this circuit.I am confused because do I have to take every necessary combination of inputs and outputs or do I have to take the longest route from input to output by deciding to take the route which has the max number of logic gates ? thx for any advice

• Looks like the longest route(s) go through 5 gates and the shortest routes go through 2 gates. – JIm Dearden May 18 '15 at 13:47

The simplest model is that each logic gate has a fixed value of propagation delay, and if you're using discrete logic gates and not operating at very high frequency, then this is probably good enough. Then all you do is add the delays of each logic gate along a path from input to output. You'll have multiple paths from input to output, so you need to find the slowest path, as this will determine the maximum speed at which the circuit can run.

Now, if you're implementing the logic circuit on say, an ASIC, the propagation delays of the logic gates are much lower than discrete logic devices and in this situation the propagation delay is much more greatly dependent on the 1) the number of other logic gate inputs the output of the previous gate is connected, 2) capacitance of the internal routing ('wiring').

For an ASIC implementation, you don't know what the capacitance of the internal routing will be as you haven't done a layout and routing of the device, so the estimated values are used. When the chip is layed out, placed and routed, the actual real values of capacitance from the physical layout are extracted and this can be fed back into a logic simulator to resimulate the logic design, and the diffence between the pre-layout and post-layout logic simulations of the circuit can be significantly different.

And there often is two propagation delays for each logic element: one value of delay for a rising input signal, and another value for a falling input signal.

For Gallium Arsenide chips, the modelling of propagation delay can be even more complex and can take into consideration (for some ASIC manufacturers) the slew rate (the rise time) of the output of the previous logic gate.

If you're implementing the design in something like CMOS 4000 series, 74xx seriest, then a simple fixed propagation delay for each logic gate should be sufficient, if you're implementing in another type of technology (with sub-nanosecond delays), you may need to use a more complex propagation delay calculation.

As the signals take many paths from inputs to outputs in a combinatorial circuit, the propagation delay is the longest path; i.e when the output would remain static following a change in the inputs.

Different gates have different delays. For example, 2 inverters in series may have the same delay as a single 4 input NAND gate with similar drive capability.

Assuming you're implementing this in a CMOS IC, a very easy way to understand which path is the longest (in general, not just your example), is to use the method of Logical Effort.

In Logical Effort you basically model the delay as $$d=gh+p$$ where

1. d is the delay (in comparative units);
2. g is the logical effort: the ratio of the input capacitance of a gate to an inverter capable of delivering the same output current;
3. h is the electrical effort: the input to load capacitance ratio of the gate
4. p is the parasitic delay

For example (from Wikipedia): The total normalised delay of an inverter driving an equivalent inverter is

d = gh + p = (1)(1) + 1 = 2


The normalised delay of a two-input NAND gate driving an identical copy of itself (such that the electrical effort is 1) is

d = gh + p = (4/3)(1) + 2 = 10/3