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We now use SCANWORKS Boundary Scan Tool from ASSET to make Ethernet SWITCH's manufacturing test. But in almost all PHY chips from broadcom corp, the MDI interfaces are "Linkage" bits. It means that there are no Boundary-Scan Cells(BSC), so we could not access them through JTAG interface. Is there any other method,except function test(because it needs more complicated firmware), to test MDI interfaces between the PHY chips and RJ45 connectors while manufacturing test? Thanks.

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  • \$\begingroup\$ Aren't MDI pins analog pins, are they? JTAG is for digital pins. \$\endgroup\$ – Paebbels May 19 '15 at 5:03
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    \$\begingroup\$ MDI pins are digital.But 1149.6 Ac-JTAG is not supported on MDI pins. And i don't know why, maybe because of isolation transformers between PHY and RJ45 connectors? \$\endgroup\$ – Steven Chen May 21 '15 at 5:45
  • \$\begingroup\$ I looked it up: Ethernet is using PAM on it's MDI pins. So it's a discrete but analoge signal. GbE -> 4D-PAM5 -> +2, +1, 0, -1, -2 volt. \$\endgroup\$ – Paebbels May 22 '15 at 1:50
  • \$\begingroup\$ Steven, it's not supported because they are not digital in the sense that you're talking about. Yes, they have discrete levels and they present a signal discrete in time, but to decide whether they behave correctly or not, it is not enough the check the voltage level. A proper manufacturing test would most probably involve attaching an external RJ45 loopback connector and exercising the transmit & receive logics through the MAC. \$\endgroup\$ – Laszlo Valko Jun 14 '15 at 18:41
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As for a 100BASE-TX PHY you can use an approach like this:

enter image description here

You need to physically loop the MDI at the RJ45 jack and then generate test patterns on TX path to the PHY TX path internal logic (i.e. digital and analog logic circuits), receive patterns at RX path---writing and reading the appropriate boundary scan cells (BSC) correspondingly---and compare them (patterns).

In 1000BASE-T case, you need a compatible link partner organizing the remote loop.

Also, the MDI circuits are analog (@Paebbels is right in full here), differential, and they reach out the RJ45 jack pins not direct but thru a transformer with a center frequency of about 30-35 MHz which are unreachable to be generated from JTAG boundary scan even as digital waveforms.

IMO, upgrading the firmware is simpler than using the boundary scan there.

If you need to test a switch IC with integrated PHYs, you need an external test pattern generator/receiver/comparator with internal loopbacks in each tested PHY path. I see no place for and/or advantage of JTAG BS there too.

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  • \$\begingroup\$ Many thanks to all. Maybe i should try external loopback test. \$\endgroup\$ – Steven Chen Jun 24 '15 at 3:16

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