Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get them.

To initiate a start sequence, What do I do? I know I want to drive SDL low while SCL is high. But I do not have much idea how I should code.

process(Start)

begin

if Start='0' then

ACTIVE='0';

else

SCL='1';

SDL='1';

SDL='0';

ACTIVE='1';

end if;

end process;


Is this the way,my start sequence initiation should be? Should I add anything else?

Besides more importantly, How am I supposed to wait for an acknowledgement?

• I hope this comment is not considered rude, but I think you should first learn how VHDL works and how it can be used to describe hardware. So you can take a class that teaches HDL 'programming' or read a book/tutorial. If you have solved to describe simple structures like counters, FSMs or decoders in hardware, you can try to describe more advanced modules for bus protocols like your requested I²C. Besides that, OpenCores has free I²C cores ready for use. – Paebbels May 18 '15 at 20:58