Do If else have priority in verilog?

I have some query about the priority of if else in verilog. For example.

  If (a)
b
else if c
d
else if e
f
else
g


At here, those a,b,c...g are all searched ? How do those have priorities in if~else in verilog?

• What do you mean by 'searched'? There's no precedence, or at least it depends on what b,d,f,g are. – Vladimir Cravero May 19 '15 at 8:25
• @Vladmir Cravero How does it synthesis? – gmotree May 19 '15 at 8:38
• They're all synthesised, provided a/c/e aren't compile-time constants. – pjc50 May 19 '15 at 8:46
• @ pjc50 I meant as gate. – gmotree May 19 '15 at 9:03
• Well. I beg to differ. AFAIK (and pls correct me if I'm wrong), if else construct infers a 'Priority routing Network', with the outermost if carrying highest priority. All of it is synthesized using a ladder of multiplexers (2:1 Mux I believe). – Plutonium smuggler May 19 '15 at 9:46

An if-else construct infers a priority routing network. Following example is taken directly from a verilog book :

if
(m==n)
r = a + b + c ;
else if (m > n )
r = a - b ;
else
r = c + 1 ;

The circuit is as shown :

As you can see, the outermost if is given a priority in the sense that it is routed first if a match is found, bypassing others.

• Thanks . There are priorities in there as cuicuit. First m and n equality check then m and n size check. – gmotree May 19 '15 at 10:17
• Yes. And finally a default case when none of the above exists. – Plutonium smuggler May 19 '15 at 10:21
• Mind giving a reference to the book? – Dzarda May 19 '15 at 10:25
• Added the link to the book. – Plutonium smuggler May 19 '15 at 10:29
• Should the synthesis tool recognize the three cases as mutually exclusive and be able to do one parallell mux? – Moberg Dec 3 '19 at 22:19