I have some query about the priority of if else in verilog. For example.

  If (a)
  else if c
  else if e

At here, those a,b,c...g are all searched ? How do those have priorities in if~else in verilog?

  • 1
    \$\begingroup\$ What do you mean by 'searched'? There's no precedence, or at least it depends on what b,d,f,g are. \$\endgroup\$ May 19 '15 at 8:25
  • \$\begingroup\$ @Vladmir Cravero How does it synthesis? \$\endgroup\$
    – gmotree
    May 19 '15 at 8:38
  • \$\begingroup\$ They're all synthesised, provided a/c/e aren't compile-time constants. \$\endgroup\$
    – pjc50
    May 19 '15 at 8:46
  • \$\begingroup\$ @ pjc50 I meant as gate. \$\endgroup\$
    – gmotree
    May 19 '15 at 9:03
  • \$\begingroup\$ Well. I beg to differ. AFAIK (and pls correct me if I'm wrong), if else construct infers a 'Priority routing Network', with the outermost if carrying highest priority. All of it is synthesized using a ladder of multiplexers (2:1 Mux I believe). \$\endgroup\$ May 19 '15 at 9:46

An if-else construct infers a priority routing network. Following example is taken directly from a verilog book :

r = a + b + c ;
else if (m > n )
r = a - b ;
r = c + 1 ;

The circuit is as shown :

enter image description here

As you can see, the outermost if is given a priority in the sense that it is routed first if a match is found, bypassing others.

Ref : Fpga prototyping by verilog

  • 1
    \$\begingroup\$ Thanks . There are priorities in there as cuicuit. First m and n equality check then m and n size check. \$\endgroup\$
    – gmotree
    May 19 '15 at 10:17
  • \$\begingroup\$ Yes. And finally a default case when none of the above exists. \$\endgroup\$ May 19 '15 at 10:21
  • \$\begingroup\$ Mind giving a reference to the book? \$\endgroup\$
    – Dzarda
    May 19 '15 at 10:25
  • \$\begingroup\$ Added the link to the book. \$\endgroup\$ May 19 '15 at 10:29
  • \$\begingroup\$ Should the synthesis tool recognize the three cases as mutually exclusive and be able to do one parallell mux? \$\endgroup\$
    – Moberg
    Dec 3 '19 at 22:19

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