Very odd open-drain output design

Question

I ran across a open-drain design and am baffled by the resistor between the nFET source and ground. There are only two purposes that I see it could serve.

1) It's series source termination, matching the impedance of a transmission line attached to the drain. However if this is the case, R would be better placed on the drain terminal.

2) Protection against a ground short in the event of an oxide breakdown shorting gate to source. Again, even in this case R would be better placed at the gate of the nFET.

Am I missing anything? The drain is indeed connected to a transmission line, and is pulled up by a 16V rail at the end of the cable run.

EDIT: I'll add that on the other end it's a high-Z digital input along with that 30k pullup to 16V. Also the buffer's supply is only 3v3, driving a low Vgs nFET.

^{simulate this circuit – Schematic created using CircuitLab}

Answer 1

I suspect it's designed to be a current source, not a hard pull-down. M1 acts as a source follower with R1 as the load. The IRF530 has a VT of 2-4V, so if the buffer is producing 16V, the output current would be around 150-170mA regardless of the pull-up voltage. The other end of the line could use current sensing to determine the state of the output.

That's as much as I can guess without knowing more about the rest of the system. What's connected on the other end of the line? What's the pull-up resistance? Is this a single-ended data line, or part of a differential pair?

EDIT: A low-VT transistor (which is more reasonable) being driven by a 3.3V buffer suggests a current of around 37mA. The weak pull-up would source 0.53mA at most. Since the input at the other end is high-impedance, that suggests to me that the goal of this circuit is to limit the slew rate. Instead of producing a very fast (and thus noisy) pull-down, the current sink gives a gradual rise whose rate depends on the line capacitance. This reduces the bandwidth of the signal.

For example, if the line capacitance is 100 pF:

$$\frac {dV} {dt} = \frac {i_{out}} {C_{line}} = \frac {37\ \mathrm{mA}}{100\ \mathrm{pF}} = 370\ \mathrm{\frac {V} {\mu s}}$$

$$t_{rise} \approx \frac {16\ \mathrm V} {370\ \mathrm {V/\mu s}} = 43.2\ \mathrm{ns}$$

$$BW \approx \frac {0.34} {t_{rise}} \approx \frac {0.34} {43.2\ \mathrm{ns}} \approx 7.87\ \mathrm {MHz}$$

The bandwidth is proportional to the current, so if your transistor can sink 500 mA, that would give you a bandwidth of over 100 MHz. It's not hard to radiate at that high a frequency! The formula I used for bandwidth is a rough approximation, so don't take it too seriously. The important thing is that a 10x difference in pull-down current can give you a 10x difference in bandwidth.

The weak pull-up is also interesting. It seems like the intent is for the line to stay low for a couple microseconds after it's pulled down. Based on the asymmetry, I suspect this is a reset or some kind of system-wide status signal, not a normal communications line.