I'm working on a PCB in Altium that will sit inside an assembly above another board. The board on the bottom has a test pad, but once everything is assembled it will be inaccessible. Therefore, I am attempting to add two pads to the top PCB (one on the bottom layer, one on the top) that are connected through vias around the edge (No, I cannot simply use a through-hole pad). The issue is this: In order to connect the vias to the top and bottom pads, they must all be connected to the same net. However, there is not a designated net for these pads, as they are simply fed through the PCB and are not used by it. It is a PCB-only feature and is not part of the circuit, so I don't want to add it to the schematic. How might I go about connecting these top and bottom layer pads through vias? Here's an image showing the top side of the PCB:

Top Test Pad

The bottom layer pad is directly beneath the one shown in the image.

  • \$\begingroup\$ I do not understand the problem. What you want is an unplated through hole with no pads (but only the hole). This can be easily done by a Through-Hole Via with the "Plated" option set to false and the pad size reduced to 0 for X and Y. Why can't you use this? \$\endgroup\$ – Tom L. May 20 '15 at 14:00
  • \$\begingroup\$ I'm afraid you misunderstood. I have two surface-mount test pads, one on either side of the PCB. I need to connect these (the top and bottom pads) through a via or two. I cannot simply use a through-hole pad for the test pad. However, since there is no net set for these, I am unable to connect the vias to the pads. They are both set to "No Net", so Altium does not see them as connected. I need to override this somehow so that I can connect the vias to the pads, thus connecting the top and bottom test pads together \$\endgroup\$ – DerStrom8 May 20 '15 at 14:03
  • \$\begingroup\$ I'm beginning to think I may just have to place the via in the middle of the test pad, but I really didn't want to do that \$\endgroup\$ – DerStrom8 May 20 '15 at 14:20

You can manually add a net using Design->Netlist->Edit nets, then select each pad and assign that net to it.

But I don't see why you don't want to do this in the schematic.

  • 2
    \$\begingroup\$ This is exactly what I was looking for--a way to add a net without it affecting the schematic. I ended up adding one called "Test" and used that to connect the vias to the pads \$\endgroup\$ – DerStrom8 May 20 '15 at 14:32

I see, it's not a hole but more two pads on top of each other. Two options:

  • Option 1: Design->Netlist->Edit Nets (add a dummy net - e.g. DUM1 and DUM2); You can then use this net in the PCB to assign it to your pads and tracks and vias.
  • Option 2: Draw two dummy objects in the schematic, connect them and assign pads as footprints; then transfer them to the PCB
  • \$\begingroup\$ Thanks Tom! Only reason I'm not marking this as the correct answer is because Spehro posted his answer first. The help is greatly appreciated though! \$\endgroup\$ – DerStrom8 May 20 '15 at 14:32
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    \$\begingroup\$ Yeah, he beat me on that one ;-) ... I'd still prefer Option 2 - only way to make sure you don't forget them in case of a PCB redesign. \$\endgroup\$ – Tom L. May 20 '15 at 18:05

The way I would do this would be to create a double-sided testpoint library component, and add it to the schematic for the board. By doing that you can assign both pads to be the same net in the schematic.

Alternately, you could move the test point to be accessible, if that's an option.

Lastly, if you select the pad and look at PCB Inspector, you can change the object specific property "Net" to the desired net.

  • \$\begingroup\$ The whole point was to avoid changing the schematic, so the first suggestion would defeat the purpose. The last option is basically what i ended up doing, but not through the inspector. Thanks for the suggestions! \$\endgroup\$ – DerStrom8 May 25 '15 at 2:38
  • \$\begingroup\$ Yeah, I recognize that- I wanted to include it in my answer because it's probably the "correct" thing to do, and for archival Stack Exchange purposes. \$\endgroup\$ – Tom Brendlinger May 26 '15 at 12:17

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