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So I found this very basic sawtooth generator:

http://www.radiolocman.com/shem/schematics.html?di=143990 enter image description here

I have a few questions about it:

I understand that when the capacitor C_T charges fully to a high, the inverter goes low, thereby letting the C_T discharge through the D_2 diode. But after that where does it drain? Does the inverter, at it's output, open a drain to the ground? Is it exactly like a CMOS NOT gate, where the NMOS half drains to ground?

What can I do to make the discharge faster so I can make the negative edge more vertical? Though, I don't care much about the rising upward ramp, that does not have to be linear (could be an upside-down capacitor charging plot for all I care).

Just how much frequency can I squeeze out of this sawtooth generator, say, if I'm using a 74LVC1G14 with 2.2ns propagation delay? I was thinking of using 1nF-100pF for C_T and 10-100ohm ranges for R_T... Can I go for hundreds of MHz? Or Is the high charging current (for R_T being so low) too much for the C_T to charge at a consistent time? If so, I happen to have the easy option of using a V_CC = 2.5V and V_DD = 5V.

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    \$\begingroup\$ Possibly related question about generating a 100 - 500 MHz sawtooth. Some good discussion there about the sort of components required. \$\endgroup\$
    – tomnexus
    May 24 '15 at 17:53
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the inverter goes low, thereby letting the C_T discharge through the D_2 diode. But after that where does it drain?

When the inverter output is low, the NMOS transistor of the inverter's output stage effectively connects the output to ground. You can look in the datasheet for the maximum sinking current to get an estimate of how fast it can discharge \$C_T\$.

What can I do to make the discharge faster so I can make the negative edge more vertical?

Reduce \$C_T\$.

You'd then have to increase \$R_T\$ to compensate if you want to keep the rising edge time the same.

To go really fast, the diode might become important and you might want to look for a faster-switching diode (but I haven't looked at the 1N4148 specs---it might already be fast enough).

Edit: I checked the 1N4148 specs. Fairchild specs it with 4 ns reverse recovery time. This spec doesn't slow down the maximum switching rate of your circuit, but it does limit how fast you can go and still maintain the sawtooth waveform shape (slow rising edge and fast falling edge). With this diode if you try to make your sawtooth faster than maybe 10 MHz, you'll probably see noticeable distortion due the diode's reverse recovery feature. The initial ~4 ns of the rising edge will be faster than the desired ramp rate.

Can I go for hundreds of MHz?

I would guess that 100 MHz is doable. Much higher than that is probably quite challenging if it's possible at all.

With 2.2 ns propagatin delay, 227 MHz will be the absolute limit.

Is the high charging current (for R_T being so low) too much for the C_T to charge at a consistent time?

I'm not sure what you mean by this question. You will probably see the discharge time vary a bit if the IC's temperature changes. The charging time probably has more to do with the stability of the Schmitt trigger's thresholds, the stability of Vcc, and the stability of \$R_T\$.

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  • \$\begingroup\$ I checked the "Sinking Current" you were referring to, I didn't find it under that name, but I suppose it's the same as "Output Clamping Current", which is 50mA according to the datasheet. Now, I don't know if this is a valid calculation, but t = 1nF*5V/50mA will be 100ns (V_CC = 5V)... That's way slow, isn't it?? \$\endgroup\$
    – Dehbop
    May 23 '15 at 1:54
  • \$\begingroup\$ In the TI datasheet, table 6.3, \$I_{OL}\$. Specified as 32 mA max. That's a recommended operating condition, not an electrical characteristic, so the actual short-circuit value will probably be a bit higher. But if you designed a circuit to run that way, you shouldn't count on it to last long. \$\endgroup\$
    – The Photon
    May 23 '15 at 1:57
  • \$\begingroup\$ Alright, how about feeding the output of the inverter to a PMOS and having the PMOS source from between C_T and R_T (replacing the D_2) and drain it to ground? \$\endgroup\$
    – Dehbop
    May 23 '15 at 2:02
  • \$\begingroup\$ The PMOS is unlikely to turn on very well in that scenario unless you can pull its gate below ground. \$\endgroup\$
    – The Photon
    May 23 '15 at 2:03
  • \$\begingroup\$ How about getting a depletion NMOS and an enhancement PMOS and make a higher current handling Inverter? I don't know about the delays, though. \$\endgroup\$
    – Dehbop
    May 23 '15 at 2:09

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