I have a 3"x3" 4-layer PCB where my stack up is:

Signal 1
5v Power
Signal 2

My Signal 1 layer has a few traces that carry 500 MHz on them, some high resolution ADCs, and microcontroller/usb circuitry. I have SMA connectors that are carrying the 500 MHz on to the board. Currently this will just be "open air" sitting on a test bench, but long term into will end up in a case in which everything will be contained internally.

My Signal 2 layer has almost nothing on it, specifically it has the following:

  • MCLR from programmer connector that is 0.1" long
  • SPI Data and Clock line that are both about 0.1" long
  • Negative voltage (for powering 2 op-amps) trace that is about 2" long

I feel like it is somewhat of a waste to have so much unused PCB. I am considering the following options:

  1. Fill the layer with my negative voltage rail
  2. Fill the layer with ground
  3. Leave the layer empty

Is there any benefit of one of the options over the other? What is usually done in these situations?

Some Additional Details

The system will be pulling a peak of 300 mA off of the 5v rail. While the -5v rail will only have about 2 mA load.

  • \$\begingroup\$ Is this going to be placed inside of a box at any point and have signals routed out of the box on cables and such? \$\endgroup\$
    – Kortuk
    Jul 21, 2011 at 15:13
  • \$\begingroup\$ Not sure if it's suitable- but you could use the spare space to create a prototyping area that'd make your device easy to mod / hack. If this is suitable I can make it a proper answer \$\endgroup\$
    – Jim
    Jul 21, 2011 at 15:20
  • \$\begingroup\$ @Kortuk Updated Question. \$\endgroup\$
    – Kellenjb
    Jul 21, 2011 at 15:30
  • \$\begingroup\$ @Jim probably not very helpful for this project. Only benefit I could see is breaking out some of my unused PIC pins, but don't want that if it will hurt my signal integrity elsewhere. \$\endgroup\$
    – Kellenjb
    Jul 21, 2011 at 15:31
  • 7
    \$\begingroup\$ I think you should do what the Commodore Amiga designers did and put some drawings on it. \$\endgroup\$
    – Majenko
    Jul 21, 2011 at 15:38

4 Answers 4


What is typically done in the industry in these cases, assuming that ground-fill practices as shown in other answers does not provide significant benefit, is something called thieving.

Thieving consists of covering large expanses of unused outer layers with a pattern of shapes, usually diamonds or squares, disconnected from one another. Thse shapes are kept away from other features, such as holes, board edges, or traces. The sole purpose of thieving is to improve manufacturability by ensuring a constant PCB thickness given any particular area on the board, say, half a square inch.

Without thieving, the rollers that are used to laminate the layers together will not exert as much force on the copper-starved areas, which could lead to delamination (looks like light spots inside the board).

  • 2
    \$\begingroup\$ How is this different from an (unconnected) copper pour? \$\endgroup\$
    – stevenvh
    Jul 23, 2011 at 10:36
  • 6
    \$\begingroup\$ The difference is that thieving is a bunch of small pieces of copper not connected to each other. This prevents eddy currents from forming, generating heat and sapping power, and prevents a source of parasitic capacitance. (Everything that plane is near is connected to it with stray capacitance, creating a crosstalk path. This is not a problem for a ground fill because the latter just looks like stray capacitance to ground with no significant crosstalk.) \$\endgroup\$ Jul 23, 2011 at 12:24
  • 1
    \$\begingroup\$ And the average copper density is made close to the general circuit area copper density so the pre-preg epoxy will have the same amount of copper and gaps to flow into. Solid copper is just as 'bad' as no copper for an internal layer. Top layer can be a solid (sometimes a soldermask forming a tinned grid) or grid pour if a shield is desired. The grid has closer thermal properties to the circuit areas a benefit during soldering and will not pick up as much solder when wave tinned. \$\endgroup\$
    – KalleMP
    Jun 1, 2016 at 16:46
  • \$\begingroup\$ Good points, though the solder pickup could be prevented by simply covering the grid or solid pattern with solder mask. (Frankly, if you're doing wave soldering without a solder mask, you shouldn't be too worried about quality. You'll get what you get.) \$\endgroup\$ Aug 23, 2016 at 4:42

Turn the negative power trace into a pour (small impact but you have the space).

Do a ground pour on the rest of the layer...BUT...use lots of stiching vias to tie it to the internal ground plane. Make sure there is no orphaned copper. Your goal is to "sandwich" the DC power plane on all side possible by grounds stitched together, this will minimize the RF impedance to ground from the 5V supply to keep it clean.

If the board is larger, you can also use the space to sprinkle decoupling capacitors around on this layer tying +5V to ground. Every 3/4 inch or so in grid. If the board is small, the decoupling on the ICs is likely enough.

A pour on the top side isn't a bad idea either although it depends on the layout.

Here is an example of what I mean by using lots of vias to couple the pour to the ground plane:

enter image description here

  • 11
    \$\begingroup\$ Make sure your stitching vias are not too close to each other. The usual rule of thumb is to keep them at least one board thickness apart. This is because, since currents flowing on these vias flow in the same direction, mutual inductance between adjacent vias increases the impedance of the vias involved. \$\endgroup\$ Jul 21, 2011 at 18:30

Is much of your board HF (tens of MHz, or even 100MHz)? If not, maybe you can get rid of the inner layers, and place components on both sides, so that you can route the power nets in the free space you get this way. Two-sided component placement is a lot cheaper than a 4-layer board.

Since you seem to have VHF on it I would populate it with decoupling caps, and pour a second ground plane, or power plane. If properly decoupled, for HF all power planes are at the same potential, so it doesn't really matter which net you pour here.

I also place as many test points as possible on the bottom of my boards, including pads for in-circuit programming (see also this answer of mine).

  • 1
    \$\begingroup\$ Any reason why you say ground pour instead of negative power pour like BarsMonster suggests? And of course every IC has proper decoupling. \$\endgroup\$
    – Kellenjb
    Jul 21, 2011 at 14:27
  • \$\begingroup\$ @Kellenjb - missed that negative voltage, but it doesn't matter, since it won't help you with routing. I might as well have suggested to duplicate the positive power supply layer here, because for HF all power nets are equivalent; HF impedance between \$V_{DD}\$ and \$GND\$ should be negligible if you decoupled properly. That's why I suggested to add extra decoupling. \$\endgroup\$
    – stevenvh
    Jul 21, 2011 at 14:52

--2. In this case should be the best - as distance between Signal2 & power is small, it will act like a distributed capacitor and will help with stability & EMI performance.

--3. No benefits.

--1. Too much hassle for single negative V user.

But personally I like just 2-sided boards, probably you may use few 0-ohm jumpers and it might end up cheaper to manufacture.

  • 4
    \$\begingroup\$ Why does 2 provide no benefits? Wouldn't the short distance cause good coupling of the 5v line which is used much more than the -5v line? How is 3 a hassle, it is the least work (as in no work) since it is currently how it is? \$\endgroup\$
    – Kellenjb
    Jul 21, 2011 at 14:30
  • \$\begingroup\$ @Kellenjb Hehe, that's stackoverflow renumbered my points, lol :-D Please see correct order now :-D \$\endgroup\$ Jul 21, 2011 at 15:19
  • \$\begingroup\$ #2: The capacitance is minimal. The real benefit is the reduced inductance of the ground plane, in addition to the shielding effects. \$\endgroup\$ Jul 21, 2011 at 18:32

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