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This is yet another semester project I'm stuck on. I need to implement a state machine starting from the following diagram: enter image description here

What I've managed to do so far is write this state table, although I'm pretty sure I've gotten something wrong even up to here.

enter image description here

I believe the next step would be drawing a Karnaugh map, but I have no idea how to assign the input values.

It also says I need to use a 8x4 memory, but I'll worry about that once I get to it. For the moment, I'm stuck on the K-map. Any help? Is the table at least correct?

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  • \$\begingroup\$ Are you sure you have to solve the Karnaugh map? If it says to use a memory, I would guess you would use it to implement your state machine. Basically, use current state and inputs as address bits and have your memory output the next state. \$\endgroup\$ – Jonathan Drolet May 25 '15 at 0:26
  • \$\begingroup\$ Wouldn't it just be 6, 5 variable K maps? \$\endgroup\$ – Duck May 25 '15 at 4:17
  • \$\begingroup\$ You should re-check your spreadsheet there appears to be at least one error. Line 15 you show a next state of 1 0 0 (appears correct from the state diagram) but your KB is 0 and should be 1. \$\endgroup\$ – user8352 May 26 '15 at 22:02
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The state table is over-complicated. If you use appropriate values drawn from the set [0,1,a,b] for each flop's J,K inputs, you can reduce it to only 8 entries. Which may give you some indication how to proceed with the next step.

I'll make one observation on the exercise : specifying the use of J-K flipflops may be OK for teaching - it's important to understand the fundamental building blocks. But once you see how it all fits together, it's simpler and more practical to implement the SM behaviourally, something like:

library ieee;
use ieee.std_logic_1164.all;

entity State_Machine is
   port ( Clock : in std_logic );        
end entity;

architecture Behavioural of State_Machine is

-- State could be an integer
--   type State_Type is range 0 to 7;
-- or an enumeration
   type State_Type is (s0, s1, s2, s3, s4, s5, s6, s7);
   signal State : State_Type;
   signal a,b : boolean;

begin

SM: process(clock) is

   function switch (test : Boolean; T,F : State_Type) return State_Type is
   begin
      if Test then
         return T;
      else
         return F;
      end if;
   end switch;

begin
   if rising_edge(clock) then
      case State is
      when s0 => State <= switch(a, T => s1, F => s7);
      when s1 => State <= switch(b, T => s2, F => s6);
      when s4 => State <= switch(b, T => s5, F => s3);
      when s5 => State <= switch(a, T => s6, F => s2);
      when s7 =>
         if a then 
            State <= s0; 
         end if;
      when others => State <= State_Type'succ(State);
      end case;
   end if;
end process SM;

end architecture;
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  • \$\begingroup\$ I know I'm only making my lack of knowledge even more obvious, but what are the "appropriate values from the set [0,1,a,b]? And what I've asked here is only a part of the project as a whole. This is what the full diagram looks like: link \$\endgroup\$ – Danesan Dragos May 25 '15 at 18:32

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