The state table is over-complicated. If you use appropriate values drawn from the set [0,1,a,b]
for each flop's J,K inputs, you can reduce it to only 8 entries. Which may give you some indication how to proceed with the next step.
I'll make one observation on the exercise : specifying the use of J-K flipflops may be OK for teaching - it's important to understand the fundamental building blocks. But once you see how it all fits together, it's simpler and more practical to implement the SM behaviourally, something like:
library ieee;
use ieee.std_logic_1164.all;
entity State_Machine is
port ( Clock : in std_logic );
end entity;
architecture Behavioural of State_Machine is
-- State could be an integer
-- type State_Type is range 0 to 7;
-- or an enumeration
type State_Type is (s0, s1, s2, s3, s4, s5, s6, s7);
signal State : State_Type;
signal a,b : boolean;
begin
SM: process(clock) is
function switch (test : Boolean; T,F : State_Type) return State_Type is
begin
if Test then
return T;
else
return F;
end if;
end switch;
begin
if rising_edge(clock) then
case State is
when s0 => State <= switch(a, T => s1, F => s7);
when s1 => State <= switch(b, T => s2, F => s6);
when s4 => State <= switch(b, T => s5, F => s3);
when s5 => State <= switch(a, T => s6, F => s2);
when s7 =>
if a then
State <= s0;
end if;
when others => State <= State_Type'succ(State);
end case;
end if;
end process SM;
end architecture;