You can use a J-FET but there are challenges.
The main problem is distortion. Here's what happens: the resistance of the channel (D-S) changes as Vgs changes. If the J-FET is in series with the signal, Vgs changes with the signal. There are techniques that minimize this problem but it is something to be aware of.
The next problem is repeatability. Each J-FET has different sensitivity in term of how the channel resistance changes as Vgs is varied.
One place where J-FETs are used very successfully is as the gain-control element in an audio AGC or compressor / limiter circuit. Because the Vgs control voltage is created by sampling the output signal, variations in Vgs sensitivity basically drop out of the equation - these circuits have a classic negative-feedback control circuit and the negative feedback simply compensates for the Vgs sensitivity between different parts.
For what it's worth, I'm currently working on a design that uses a logarithmic-taper digital pot (32k, 100 steps) from Catalyst / On Semiconductor. Although this part is scheduled for end-of-life this year, we will simply purchase enough parts to see the product through its manufacturing lifetime.
And, yes: using a digital pot with log taper makes my hardware design dramatically less complex and expensive.