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I am toying with designing a simple 8-bit CPU out of basic logic components. I have a fairly good idea of how my ALU and registers will interact, but the one thing I feel can use some improvement is how to toggle when a line is allowed to connect to the main data bus.

My initial thought was to use and gates to drive the bus. The output from the various lines in the ALU could all go into a set of quad-AND chips that output onto the bus. Only one set of AND gates at a time would have all of its B inputs pulled high to let it out onto the bus.

A couple of things I am unsure about: It seems wasteful to use eight full AND gates per line, when I only need one control line going in. Is there a better chip more suited to this purpose? I'm sure I could also do it with eight transistors, but I would like to stick with fairly common (and cheap) ICs.

A solution like this only lets data flow one way from the bus. Is this a problem? I think not, since I have other control lines stopping registers from loading the bus data until I want them to.

Is there a standard chip to use for a bus gate like this?

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The 74HC244 is the typical device for connecting to/disconnecting from a bus. It's an octal tri-state buffer (or rather a dual quad buffer). You'll need the tri-state feature to disconnect completely from the bus. The gates would set the bus high or low, but that wouldn't allow another device on it.

But since you're talking about a data bus you probably want a bidirectional buffer. Then you can use the 74HC245.

74HC245

You have a DIR pin to control the direction and a /OE which can make the buffer tri-state.

edit
JustJeff mentions the 74HC374 octal tri-state D flip-flop. (Note: I'll talk about the 74HC574, which is functionally the same, but has a more logical pinout.) The 74HC574 is indeed an interesting part, and a classic since the SN74xx series. While the 74HC245 will give you a tri-state buffer, the 74HC574 has a memory function too, in the form of an octal D flip-flop. Great to make registers, and through the tri-state connection to the bus you can route your data flow easily.
There's a drawback to this, however. The register's output is only available to the bus, so all communication would have to pass there, so that the bus will become a bottle-neck. Therefore I think it's better to replace the 74HC374 by a 74HC273 octal D flip-flop followed by a separate 74HC244 tri-state buffer for the connection to the bus. That way the register's output is also available internally when some other signal occupies the bus. (I don't know if there's a function compatible part with the more logical pinout. You may also use a 74HC574 with /OE hardwired to ground.)

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  • \$\begingroup\$ That looks great! I'm not sure yet how my registers will interact with the bus, but I suspect the bidirectional ones will help there. \$\endgroup\$ – captncraig Jul 22 '11 at 6:36
  • \$\begingroup\$ @CMP - in a situation like you describe - building a CPU from scratch - tri-state outputs are your friends. For example, the 74hc374 is an 8-bit register that provides tri-stateable output in the same chip. You can bus the outputs of several of these together, and just assert the OE of the one you want "on the bus". \$\endgroup\$ – JustJeff Jul 23 '11 at 16:57
  • \$\begingroup\$ It's worth noting that many CPU's in fact had registers which could only take input or send output from/to shared buses (in many cases, input from one bus; output on another). While such a design may in some cases be a bottleneck, I don't think the goal here is to compete with an i7. Note that if one wants a register to take input from one bus and be selectively output to two different buses, one could use a 74HC273 and two 74HC244's, but one could do the job with just two 74HC574's which latch the same data. \$\endgroup\$ – supercat Aug 31 '11 at 0:25
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(1) AND gates are inherently unsuitable for commoning as transparent bus buffers because if they have fully active output drivers they interact, and if "open collector" the logic inverts.

You can use open collector 2-input OR gates as single line drivers to a common bus.

If you feed "data" and "not_enable" to an OR gate the output will be high if not_enable is high and will follow data if not_enable is low.

When the output of an open collector gate is high it does not load the bus in any way. When it is low it loads the bus with a turned on low output. So, multiple open collector O gates can share the bus and only enabled ones (usually one at a time) can drive the bus. You need a single pullup to pull the bus high and any number of gates to drive it low.

(2) EDUC-8 was/is an 8 bit TTL based microcomputer presented as a multi month project in Electronics Australia magazine from August 1974 to August 1975. Even if you did not want to copy it you could learn much by looking at how it was implemented. There are various enthusiasts who have built copies in recent years.

Very extensive documentation of one user's EDUC-8 journey ... Same ... Includes details of his toner transfer PCB making of the several latrgsih PCBs and much much more.

Wikipedia EDUC-8

Links page

Some documentation

PCB image

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