# Where did the value of 0.1uF for bypass capacitors come from?

Nearly everyone recommends 0.1uF for bypass capacitors. Why this value? I assume there is no harm to using larger values so is it merely a "sensible minimum"? And if so why do people go for the minimum rather than using higher values - it seems to me you can get higher values at no extra cost.

• Even though as state higher value capacitors can be purchased at the same value, the frequency response of higher value capacitor is narrower than lower value capacitors, see electronics.stackexchange.com/questions/59325/… Commented May 26, 2015 at 13:54

Higher value capacitors will not be as effective at dealing with high frequency current drawn by the chip. Above a certain frequency a capacitor will start to behave like an inductor. The value where its characteristic changes is the series self resonance of the device: -

Thus, you'll find that on microwave devices 100pF capacitors are also present as decoupling along with the bulk capacitors. Here's an example of three capacitors decoupling an FPGA: -

The black curve is the composite impedance of all three capacitors used. Taken from here.

Where did the value of 0.1uF for bypass capacitors come from?

It's a good compromise between bulk and high frequency capacitance BUT if you are designing radios your default decoupler may be 10nF or 1nF (UHF). If you are designing really high speed digital stuff you may also use 2 or 3 different values in parallel like in the FPGA picture above.

• Could you explain why they would start to behave like inductors? Is it because at higher frequencies their impedance would lower untill the equivalent series inductance takes over? Commented May 26, 2015 at 14:10
• @Golaz - exactly - look at the 2nd graph in my answer - it shows a precise representation of three capacitors and bear in mind that a pcb track may have an inductance of 1nH per mm. Commented May 26, 2015 at 14:15
• Note closely the antiresonant peaks in the black curve in Andy's graph -- they are why it's better to use several identical capacitors in parallel than to parallel different value capacitors. (Of course, Ott explains it all quite well in Electromagnetic Compatibility Engineering...) Commented May 26, 2015 at 22:10
• In reality it's a nice round number, which is why it's so overhelmingly popular. Some people say you should match the resonant frequency with your IC fundamental frequency e.g. µCU clock speed. Other people say it makes the circuit switch faster and creates more high-frequency EMI. I believe the latter is wrong because sharp(er) edges are far beyond the fundamental frequency. Datasheet resonant frequency disregards vias and traces so in reality you'd have to experiment to get capacitance just right. Then there's the combination of the two, ~1µF "bulk" cap nearby and <100nF immediately close Commented Nov 26, 2018 at 11:39
• I am sorry, but this answer and the diagrams in it is mostly based on wastly outdated information from the 90s. The high frequency response of capacitors has nothing to do with the capacitor value, and everything to do with the capacitor package. Today, you can get 10µF ceramics in 0603 or even 0402 package. It is completely pointless to connect 100nF caps in paralell with a 10µF cap of the same physical size. See this for a much more up-to-date answer, including modern diagrams: electronics.stackexchange.com/questions/327975/… Commented Sep 19, 2019 at 12:39

Not everyone recommends 0.1uF as a decoupling capacitor, though it's a good starting point for 74HC and single gate logic. Kevegaro's answer here is a good one.

For example, for Xilinx FPGAs here is one recommendation for bypass capacitors:

They recommend 33 capacitors of three different values per device.

• Also this brings up another question I have: Why do they recommend to use multiple different values? Is it just because it is impossible to get the 100uF capacitors close enough to the device? Edit: Never mind, Andy's answer answers this. Commented May 26, 2015 at 14:56
• Yes, Andy answers this quite thoroughly! Commented May 26, 2015 at 15:05
• Odd recommendation with the three values -- having a reservoir cap per rail and then at least one 0.1uF per power pin would make more sense than trying to economize on caps at the expense of risking a failure due to antiresonant peaks, especially for a programmable device where the clocks may be well...anything! Commented May 26, 2015 at 22:11

The recommendation to use multiple values, such as 100nF + 10µF, is from the 90s and 80s when 100nF was the highest readily available ceramic capacitor with decent high frequency response. The 10µF capacitor would be an electrolytic or tantalum capacitor with poor high frequency behavior.

That has changed completely today. Now you can easily buy 10µF ceramics in 0603 or even 0402 packages. For ceramic capacitors, the high frequency response has nothing to do with the capacitor value, and everything to do with the package size of the capacitor.

With modern capacitors, it is usually pointless to connect a 100nF in parallel with a 10µF.

You can easily see in the diagram below that modern high value ceramic capacitors are just as good as low value capacitors for high frequencies, as long as the package size is the same. (The small negative dips are the resonance frequencies. You do not want to rely on the resonance frequency for decoupling capacitors, so those dips should be ignored)

(Image source: Analog Dialogue Sep 2005 - A Practical Guide to High-Speed Printed-Circuit-Board Layout)

• That said, the most economical choice is often to use a bunch of 100nF capacitors near the load to get the ESL value it needs, and one or two 10µF bulk capacitors elsewhere on the board. But if physical size is your primary concern, then you could be better off using only µF caps. If you look in an iPhone for example, you will not find any 100nF capacitors. They have determined that the physically smallest way to reach the ESL and ESR performance they needed was to only use larger value capacitors. Commented Jul 5 at 8:35

Andy's explanation is beautiful and in-depth. If you find it difficult to grasp, it may help you to visualize how decoupling works in simple terms. In your mind imagine a 3D view of your board, it has a load (ICs, etc) and a power source. The load may suddenly "request" more current from the power supply however it takes time for current from the supply to reach the load over the trace distance and trace resistance. Also the built-in resistance of the supply itself or time for a switching supply to detect the new current demand and adjust (supply bandwidth) is a factor. In short, a power supply does not supply current instantly, it takes time. So imagine the load sending a message to the power supply it needs more power and the supply then ramping up to more current and sending that current out along the delivery route (trace or power plane).

As the load is waiting for the current to arrive it has no choice but to pull the voltage down to compensate for the "missing" current. It has to obey the law V=IR, the load decreased it's resistance (R) to "indicate" it needs more power, there was no more current immediately available so I stays the same, so V has to decrease to compensate.

So how do we solve that? We put little capacitors close to the load. These capacitors are little "charge banks" that the load can quickly withdraw from during excess demand, quicker than waiting for the current to come out of the supply. Why is it faster? Because the distance between the capacitor and load is shorter, and because the built-in resistance of a capacitor is much smaller than a power supply. If "I" is immediately available then "V" does not need to compensate - everyone is happy.

Although much faster than power supplies, capacitors also take time to "discharge" and provide power to the load in proportion to their internal resistance which increases with capacity (farads). So in short, larger capacitors take longer to supply the needed current. So you want to choose a bypass capacitor that is fast enough to respond to the load, but also holds enough charge to fill the demand while current from the power supply travels to the load.

So where did the value of 0.1uF for bypass capacitors come from?


As previously mentioned, for common logic it was a good trade-off between response time and capacity requirements of the bypass caps to the load demands. You could get out the calculator and find out exactly what the best value is but there are also Bill of Materials costs to consider. If you tune each bypass capacitor to it's load you'll end up with many more line items on your BOM and it will get costly very quick! 0.1uF for most logic circuits or for high speed circuits 0.01uF is usually a good choice. Save money in your BOM where you can within the limits of the application.

For loads that frequently change current demand (high frequency loads) there are other ways of getting around the response time versus capacity problem of bypass capacitors. You can:

1. Use a better power regulator with higher bandwidth so it doesnt take so long to get power from source to load.
2. Put two capacitors in parallel. Two resistors in parallel decrease total resistance and it is no different with internal resistances of capacitors. Therefor the combined capacitors have increased capacity and increased response time!
3. You could use parallel caps of different capacity, big buddy and little buddy. So one might be 0.01uF and another 0.1uF. The first having quick response and the second lagging a bit in response but providing current for a longer duration.
4. You can also distribute capacitance in your circuit but not necessarily at the load point. This charge reservoir response is faster than the source supply so you can then use smaller bypass capacitors at the load knowing that your distributed charge reservoirs will pickup the slack in the supply.

This is a simplified view of everything. There are more factors especially in high-speed circuits. But if you can imagine the basic electric principles at play in your circuit as a dynamic system of supply and demand a lot of the "best practices" we read about become common sense. A simpler analogy might be Amazon's supply chain. Their goal: supply items as quick as possible anywhere in the US. Their solution, warehouses close to every city, less response time getting items out of the warehouse and in the truck. Next is drone delivery. It's a logistical battle of supply and demand and trade-off over response time and capacity versus size of each distribution node and costs!

A really good video from EEVBlog on factors for parallel capacitors: https://www.youtube.com/watch?v=wwANKw36Mjw

• Just to follow up briefly on your suggestions: 1. is helpful for cutting down on reservoir capacitance needs albeit not quick enough to deal with the spikes produced by most digital switching, 2. is a very good one, especially when scaled to 10 or 20 caps for a device instead of 2 or 3 (for large chips, my rule of thumb is 1 100nF cap per power pin), 3. isn't so great because of antiresonant spikes that can create noise peaks on your board (look closely at Andy's graph again!), and 4. is a surprisingly good suggestion (look up "Buried Capacitance" technology for an exceptional example) Commented May 27, 2015 at 22:32
• Good simple answer, though from Andy's answer it seems like it is actually the inductance that is the limiting factor, not resistance. Commented May 28, 2015 at 13:16
• Yes. I didn't touch on inductance in my analogy but it definitely matters. Really, I should be using the word impedance in place of resistance above since that is a factor of the inductance, resistance and frequency...resistance just sounds simpler to people. Resistance being 0Hz resistance and impedance being resistance when at a certain frequency. Commented Jun 7, 2015 at 0:13