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I was given this circuit. Can somebody explain how this works to create the negative voltage and to lock in the voltages for the source switching?

I need to make +-15 somehow. How would I scale capacitors and change this?

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Does anyone have any insight as to how to make this work for 6mA on each rail?
I assume the clock signal has to be adjusted.

A simple means of providing 6mA per output has been requested.
This is able to be calculated from the notes below but these are "a bit dense" so here is an outline, with details of operation in the following material.

The simple answer is that power out rises about linearly with frequency and with the values of C101, C102 & C103 provided that the opamp can cope. But Vout will almost certainly not reach +/- 15V under load.

As noted below "Use of a very modest inductor based switching power supply would be easier. Unless there was a compelling reason to use a switched capacitor supply, the use of an inductor based supply would be vastly easier to implement. Even if power levels desired are achieved with this circuit the requested Vout +15V and -15V will be reached only under unloaded conditions.


Maximum possible power transfer is given by
Power = 1/2 x C x (Vmax^2 - Vdischg^2) x f .... 1

Where Vmax is the capacitor maximum charge voltage, Vdischg is the voltage it discharges to per cycle, f = frequency and C = capacitance of the switching capacitor.

+13V out As shown the circuit is claimed to give 0.6 mA at +13V and 0.1 MA at -13V.
So the request is for an increase of about 10 times the V+ current and 60 x the V- current. It's likely that "there will be problems" without a major redesign.
Use of a very modest inductor based switching power supply would be easier. However.

The two 'obvious' parameters that can be changed are C and F. Changing Vdischg will also give more power but will also lower the output voltages which are already lower than being asked for. So

Present clock is about 333 kHz.
The opamp may tolerate this being increased to 1 MHz and may be more.
A more detailed examination of the spec sheet is required.
C101 is 0.01 uF. Increasing this to 0.1 uF nominally increases Iout by 10x if the opamp can handle the load.
So - Increase C101 to 0.1 uF, Increase input frequency to 1 Mhz. Simulate (or build) and observe.

Vout + max is about 2 x V+in - 2 x Vdiode or about +15V at zero load.

Negative supply - -13V. It is not obvious why the supply is as low as shown - unless this is what is required rather than what is possible. The two stage supply will lose at least 4 x Vdiode so Vout max is perhaps -14 to -15V unloaded. Increasing C102 and C103 to 0.1 uF or beyond increases output. The real world ability of the opamp to supply the relatively modest current at this frequency needs to be checked.

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Detail:

Op amp output swing 0/+8V.
LHS (left hand side) of caps C10x also swing +8/0.
When a cap is square wave driven the rhs instantaneously tracks the lhs when a step is applied and THEN is altered in voltage by attached circuitry.

Assume OAO low to start. Assume diodes ideal for now (Vdiode on = 0)

OAO low C101 rhs charges to +8V from +8V supply

OAO high C101 rhs rises to OAO 8V + 8V =1 16V
D101 conducts to provide up to +16V onto C107
BUT as C107 >> C101 (1100 nF versus 10 nF) it will take many cycles to charge C107 to +16V.

As Vdiode is say 0.5V when charging (D102) and discharging (D101) then:
C101 charge = 7.5V.
So C101 rhs with OAO at 8V = 15.5V
So D101 out = 15V max.
Which is > unloaded +13V required = OKish.

Max energy transfer for full cap discharge = 1/2 x C x V^2 x f.
For Delta V on cap from Vmax to Vdischg energy transfer max -=
1/2 x C x (Vmax^2 - Vdischg^2) x f

Pulse period (lhs of diagram = 2.8 uS + 0.1 + 0.1 rise and fall = say 3 uS.
So freq ~~~ = 333 kHz.
Say cap charges to 7.5V and discharges to 7V (this is NOT related to diode drop - just happens to match).
Pmax = 1/2 x 10 nF x (7.5^2 - 7^2) x 333 kHz = 12 mW.
Desired load as shown = 0.6 mA at 13V = 7.8 mW.
So target = 7.7/13 = 60%.
I'd say that was "hopeful" Just increasing C101 will increase power level as long as opamp can source the current with minimal voltage drop.

Bottom part works similarly but wityh reversed diodes to give -ve supply AND has two stages. C102 drives a -8V out stage (really -7V max).
THEN this - voltage is used as feed voltage for next stage. At most it can give about
-7 -8 + 2 diode drop or about -14V at no power.

OP262 op amp data sheet here - this looks a good choice. Rail to rail output, good drive mA, 15 MHz and 13V/uS slew.

$5.56/1 Digikey.

Vout per stage ~= Vswing_AC_in + Vfeed_DC - 1V.

Must rush off alas. More later maybe.

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  • \$\begingroup\$ Does anyone have any insight as to how to make this work for 6mA on each rail? I assume the clock signal has to be adjusted. Very new to this. Thanks! \$\endgroup\$
    – jonnyd42
    Jun 2, 2015 at 17:25

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