I'm trying to generate a 40MHz clock on a 100Mhz FPGA and I find it a kind of struggle using Verilog code.
I redirected the clock to a pin to check the 100Mhz functionality:
assign pin1= clock; //gives me a 100MHz clock assign pin2= ~clock; //gives me a 100MHz inverse clock
reg clock1; reg [4:0] prescaler1; always @(posedge clk) begin if(reset==1'b1)begin clock1=1'b0; prescaler1=2'b0; end else begin if(prescaler1==2'b01) begin clock1=~clock1; prescaler1=1'b0; end else begin prescaler1=prescaler1+1'b1; clock1=clock1; end end end
That gives me 50, 25, 16.66 and 12.5MHz depending on whether the prescaler set to 0, 1, 2, 3.
Is there a trick to doing it?
It is a Zedboard Zynq-7000 Z-7020. XPS lets you assign 4 PL fabric clocks but I believe they have to be in multiples of 33MHz.
What's the difference between ARM_PLL, IO_PLL and DRR_PLL?