I was just watching this video: https://www.youtube.com/watch?v=ti5jD7Q7BSA At 25:10, he says that if you have an active high SR latch with initial conditions S=R=0, Q=1, and you set S to 1, Q will still remain 1. Can someone explain why this is the case? A NOR gate with input 1 and 0 has output 0, so shouldn't that set Q to 0?
There are two types of SR Latches:
NOR (left) and NAND (right) based
In case of NOR SR latch if Q output is 1 and you set S to 1, when looking on the schematic you can conclude that output of bottom NOR gate is 0 (inverted 1), but R input on the upper NOR is also 0 so it gives you (inverted 0) 1 on the output of top NOR and Q state has not changed.
In case of NAND SR latch if Q output is 1 and you set S input to 1, Q state change from 1 to 0.