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Is it possible (effective) to do oversampling and apply extra Moving Average Filter with a delta-sigma (ΔΣ) analog-to-digital converter (ADC)?

More detailed: The ADC (ADS1258) I chose has an effective resolution of 19.5 Bit at a sampling rate of 23.7kSPS/Channel. I need that high sampling rate for a feedback; however the final output can be at data rate of 500 to 1k Hz and must have more effective Bits (22 – 24 Bit).

I know that the ADC applies internally 5 cascaded windowed moving average filters which make it very inefficient to gain further resolution Bits (The noise is than correlated). But then there is the down sampling applied at the end of the ADC.

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If I read your question correctly you can decimate after your ADC and get resolution gains (as you can do with any ADC). For each additional bit of resolution to be gained, you decimate/average 4 samples so, 23.7k divided by 4 gets a decimated rate of 5.925k and the resolution increases from 19.5 bits to 20.5 bits.

Decimate by 4 again and you get a sample rate of 1.48125k and a resolution of 21.5 bits. The extra half bit of resolution can come from decimating by a further 2:1.

Here is an Atmel document that explains it and I hope I haven't misunderstood your question.

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  • \$\begingroup\$ you got the question right (mostly). Thank you for the answer. But as the Atmel document says, the noise needs to be white noise and that is where my real question starts. Is the noise at the output of the ΔΣ ADC sufficient? The ΔΣ ADC already applied serveral moving window average filter. \$\endgroup\$ – Ren May 29 '15 at 12:32
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    \$\begingroup\$ My estimation is that if the ADC has already successfully decimated from a single ΣΔ bit-stream using filters to 23.7k (and improves SNR etc) then doing some more after the ADC will also yield reasonable results. I don't expect the noise shape to be HF-pronounced (as per in the ADC) and hence get better process gain than the decimation in the ADC BUT, I would reasonably expect the noise to be fairly flat across the spectrum of question at the very least BUT who knows what sample-synchronous artefacts are lurking? \$\endgroup\$ – Andy aka May 29 '15 at 12:51
  • \$\begingroup\$ Are you in a position to analyse the noise spectrum coming from the ΣΔ ADC? \$\endgroup\$ – Andy aka May 29 '15 at 12:54
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    \$\begingroup\$ Exactly -- the nature of sigma delta makes this less of a slam dunk. If it were straightforward, you'd think that you could buy higher order stable sigma deltas that would give you the ENOB you need -- but you can't. I'd proceed with caution. It's easy to fool yourself into believing you have better resolution than you really have. \$\endgroup\$ – Scott Seidman May 29 '15 at 13:00
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That's a high resolution to shoot for. The sigma delta is, by it nature, oversampling already, and I suspect you'll have a difficult time getting better resolution, but it will depend upon the nature of your signal.

Do you really need 22 bits of dynamic range, or can you simply amplify?

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  • \$\begingroup\$ The target signal amplitude is about 2μV. To analyze the target signal, 100 Step resolution of the 2μV are desired. As a result for an effective 21 Bit resolution the target signal needs to be amplified by Factor of 80. Low gain is preferred due to the distortion with much higher amplitude than target signal. \$\endgroup\$ – Ren May 29 '15 at 12:47
  • \$\begingroup\$ @Ren, how about a more appropriate reference voltage on your ADC, along with some more modest amplification? If your signal is not stationary, oversampling and decimating probably won't buy you the effective resolution you want without using some more advanced techniques, like adding the noise referred to in the docs Andy points to. \$\endgroup\$ – Scott Seidman May 29 '15 at 12:56

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