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I am trying to build serial-in shift register (non cycled) based on synchronous RS flip-flop, but i'v got a problem with synchronization. My clock generator was configured to long on period and short on period. In first case all flip-flops are setups to value that comes to first flip-flop in scheme (example at first time chart). It's looks obliously, because S-RS is level-triggered flip-flop. In short on period case register gives right result exclude one case (between 20ns and 25ns on second time chart). Are there ways to solve this problem, without changing or adding a flip-flop than that used in the scheme? Scheme Time chart Time chart - long period

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I believe your problem comes from the clock signal you're using. Its positive pulses last for about 100 ps or less, and the flip-flops probably don't have enough time to react to them, which leads to sporadic errors.

Find the maximum switching frequency in the spec of your flip-flops. It is usually given for a clock signal with 50% duty cycle, so you can take half of the period and assume that positive pulses of your custom clock signal cannot be shorter than this value.

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  • \$\begingroup\$ Thanks for answer. As I mentioned in first post, in case of half-period of positive pulse cause wrong result - all flip-flops sets to input signal, because synchronization is performed by level, not by edge. A edited my post and add new time chart. \$\endgroup\$ – iRomul May 31 '15 at 1:50
  • \$\begingroup\$ I didn't get that, since the title says "sync flip-flop" when in fact you're using async latches. Anyway, it's a bad idea to build sync circuits with async components. A shift register needs D flip-flops, and you need two latches to implement one flip-flop correctly. \$\endgroup\$ – Dmitry Grigoryev May 31 '15 at 17:41

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