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I had always thought that if an IC is grounded to the ground plane then connecting a decoupling capacitor to VDD on one side and straight to ground plane on other side as shown below is acceptable:

Is this wrong?

However as I understand this poorly spelled guide from the depths of the internet tells me I was wrong all along and the correct way is to run a trace from the IC ground pin to the capacitor and THEN connect to the ground plane:

Is this right?

I believe I was using d) which is somehow wrong. Can anyone more experienced shed some light on this topic, which one of these is the preferred method? Thank you.

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  • \$\begingroup\$ d) is wrong and f) is correct - see the explanations. Why didn't you take any notice of them? \$\endgroup\$ – Leon Heller Jun 1 '15 at 10:43
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    \$\begingroup\$ @LeonHeller I'm not convinced the sentence "VCC and GND lead to supply noise current flows not via DeCap. DeCap has not effect" is a full explanation for everyone in the world. Most people see a plane as just a short circuit, even some professionals, so especially for D, it's very lacking. That a, c and e are bad are more obvious, b in a lesser amount. As such I find this question valid. \$\endgroup\$ – Asmyldof Jun 1 '15 at 10:51
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    \$\begingroup\$ I agree with Asmyldof. This is an important question, and those examples are stupidly unclear, the entire point of that capacitor to to consume the rippling noise, and to be a charge storage for high intensity loading of the IC. Ask away. \$\endgroup\$ – ARMATAV Jun 1 '15 at 15:21
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    \$\begingroup\$ For what it's worth, the comments on examples 'a' and 'c' in the image are BS. I wouldn't put too much trust in the source where you found the image. \$\endgroup\$ – The Photon Jun 1 '15 at 16:11
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It is to do with the direction the current flows, how hard that is and what that can cause.

What happens with d, for example, is that switching noise from the uC can take reasonable current spikes. These currents are injected directly into the ground plane and its set of capacitance and inductance. At some stage that energy is partly compensated by the decoupling capacitor, but it will be too late. The spike is already in the ground domain and the current might induce a running spike or oscillation along the ground plane, because it's not simply a metal plate. It has a very difficult set of mathematical equations going on inside it regarding its own inductance and capacitance to other copper areas.

Granted an actual ring on a ground plane is not easy to achieve, especially with a small loop, but better to have a bogeyman that's not likely to ever happen, than assume all sunshine every day.

You want all noise spikes to always see the capacitor before it sees anything else, on both tracks, so you know it will prefer taking energy from the capacitor rather than your power planes and inject its noise directly into the rest of your system.

EDIT:

There are (limited) reasons to use D. In the case of your first picture might be one. If the traces need to be long for your components to see the cap directly, the via to the plane might be the lesser of two evils. A long trace will pinch off the switching current available to the uC/complex-chip. And it might use those currents to generate noise back into the chip, if you happen to run it below the substrates (rare as it may be). But in general the rule of the chip seeing the capacitance first on both traces is a good one and most uC/uP/FPGA type devices have their pins such that this is possible with very short traces. Some parts of the ATTiny and PIC type families excluded, but what do you want for a single $?

Although, you can see that the Tiny261-family has a lot of AD and also chose to put the power pins next to each other for both domains. Coincidence?

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    \$\begingroup\$ I must say, that at least two times i was advised by EMI consultants in certain cases to remove the trace connecting the cap to IC leads, and only have vias instead. \$\endgroup\$ – Gregory Kornblum Jun 1 '15 at 11:00
  • \$\begingroup\$ @GregoryKornblum Okay, I'll add a caveat. \$\endgroup\$ – Asmyldof Jun 1 '15 at 11:11
  • \$\begingroup\$ It's some legal notice, right? No need, i am not arguing :) \$\endgroup\$ – Gregory Kornblum Jun 1 '15 at 11:13
  • \$\begingroup\$ @GregoryKornblum You made a point and I found it helpful for posterity to include it in my answer. See Edit. I'm not as courteous today as I'm a bit stressed, I could have used more words. \$\endgroup\$ – Asmyldof Jun 1 '15 at 11:15
  • \$\begingroup\$ Hope everything is fine. \$\endgroup\$ – Gregory Kornblum Jun 1 '15 at 11:22
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It all depends on specific component switching characteristics and specific PCB. For most designs it will not matter at all. For designs where it matters, wher the switching frequency is very high, you should understand why are you even bothering with the decoupling capacitors. Once the clock edge occurs, many transistors inside switch at the same time, and to work properly all of them need the VDD supply to remain stable, otherwise their outputs will not work well. And since all of them are actually driving other tansistors gates, the initial current is quite high. So the current pulse comes from the decoupling capacitor. If the trace inductance between it and IC pin is high, it will not allow sufficient current. This is by the way why sometimes you will need 0201 caps- smaller case has smaller inductance. Now, vias usually have lower inductance that several mm trace. Plane has almost zero inductance, if there is not much holes in it.

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  • \$\begingroup\$ Ah, I see, this part seems clear now. Now you mentioned that the inductance of vias is much lower than of traces. Does it mean that in situations where long tracing around components, pins or other traces is necessary to connect some pins it's more worthwhile to just add some vias into the ground plane and add a small shortcut between the pins, or is it preferred to leave the ground plane as intact as possible and trace around everything in one layer as long as it's doable, even if it makes the traces long? \$\endgroup\$ – I have no idea what I'm doing Jun 2 '15 at 6:50
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    \$\begingroup\$ Wow, that's a million dollars question. You need to maintain balance of intact plane and short traces. Traces may be used in some cases more widely, where you don't expect fast switching, and where you use thick trace, and where you have a capacitor. On the other hand, plane is not busted by a single hole, so it's much about your common sense. And of course you will see, that in most designs there is not much difference. Close decoupling capacitor is usually enough. The design must be extremely careful for 0.5GHz chips and higher, below that just use your common sense. \$\endgroup\$ – Gregory Kornblum Jun 2 '15 at 11:59
  • \$\begingroup\$ And always reserve time and money for second layout. \$\endgroup\$ – Gregory Kornblum Jun 2 '15 at 12:03

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