I'm not familiar with Xilinx's tools, but I am with Altera's, so I'll tell you about theirs. Xilinx and others shouldn't be too different.
The first thing you will need to do is learn Verilog. This will make your head hurt because Verilog (and the somewhat similar VHDL) was first designed as a simulation language, and many constructs (like
#5 which means "wait 5 time steps", a time step usually being a nanosecond). So there are a lot of restrictions that you have to keep in mind to make your Verilog code synthesizable, i.e. compilable into a bitstream for an FPGA.
The biggest shock, though, is that what you write in Verilog (and VHDL) is the behavior you expect from the system, and the compiler infers the proper logic from your description. If you're not careful, you can get lots of nasty bugs from this.
For example, a D flip-flop looks like:
always @(posedge RESET or posedge CLK)
Q <= 1'b0;
Q <= D;
This describes how a DFF works, and the compiler has to analyze it and figure out you want a DFF. The
@(...) is called a sensitivity list, which is a list of signals that trigger a reevaluation of the code block; thus, in this block,
Q only changes if there is a rising edge on
CLK (this is for an active-high reset). If you forget something in the sensitivity list (which should contain all the right-hand-side variables without any
negedge modifiers for a combinational logic block) the compiler will synthesize latches as needed rather than call an error. Crazy, but it's how it is, because Verilog was originally a simulation language that hid (and thus did not require) implementation details. VHDL is the same but much more verbose.
Finally, a new version of Verilog called SystemVerilog was released a few years back which makes writing synthesizable code much, much easier. If at all possible, learn this language, as Xilinx ISE and Altera Quartus II both support it. The main problem is the utter lack of good reference material.
The SystemVerilog version of a DFF cleans up a couple small things:
always_ff @(posedge RESET, posedge CLK)
Q <= '0;
Q <= D;
Note that the signals in the sensitivity list are separated by commas. This is because
or was confusing since
and couldn't work there. Also note the replacement of
1'b0 (a single
0 bit) with
'0 (a symbol that expands to however many
0 bits are needed based on what it is being assigned to; much more flexible with parameterized modules). Finally, note the replacement of
always (which could be used for anything; combinational logic, latches, and flip flops) with
always_ff which requires the contents to synthesize to flip-flops. There's also an
always_comb which eliminates the sensitivity list, since it just works out the sensitivities from the inputs to the block.
Altera's design software is called Quartus II, and you'll be looking for the Web Edition. (The subscription editions are rather expensive and only needed for the fastest or most recent FPGA models.)
The sad part is that I haven't found a good book on the subject. What I've learned I got by piecing things together from multiple sources, such as Verilog books which don't do a good job of telling you what is synthesizable and what isn't, and example code. Quartus II has a "insert template" command that inserts template code for several common structures, from D flip-flops to state machines.
Once you've implemented your processor in Verilog, you need to build it. For the time being, let Quartus choose the chip (you have to choose the family; I'd recommend the Cyclone IV) and the pinouts. Once it biulds, you'll know how much chip you need. It will tell you how many logic elements, flip flops, RAM bits, etc. you used. Make sure you're not over 50% on any of those; if you are, look at the chip the compiler chose and manually select the next bigger (in logic elements) chip which has at least as many pins, and repeat until you get utilization under 50%.
Then go shopping for a demo board that has a chip at least as big as the one you finally built with. Check to see that it has the peripherals and/or I/O connectors that you'll need. It's not uncommon to build a daughtercard that plugs into an expansion connector to provide any missing hardware.
Now that you've picked your hardware, figure out the real pinouts and use the Pin Planner to put the right signals on the right pins. The demo board will have a user's guide that tells you which pins are wired to what devices or connector pins on the demo board.
Once you get the pinouts set, build it again so it uses the pins you want. Bear in mind that some signals like system clocks will need dedicated input pins (so they route straight to the internal PLLs).
Use the programmer to download your design directly into the FPGA (that shift register I mentioned a while back). Now you're in the familiar edit-compile-run debugging cycle. Beat on it until it works.
Once it works, you can use the programmer to download the code into the onboard configuration device so that your program will load and run on power-on.
This was pretty long, and I hope it helped some. There's a lot to learn; it's not like learning a new programming language as much as it's like learning a new programming paradigm, e.g. moving from procedural to functional languages. Verilog is a simultaneous language; most of the code is always executing.