I recently went on a long voyage of self-teaching logic design. The final product of this is a functional 16 bit CPU that works exactly as designed in a simulator. Now I've just started looking into the possibility of putting it into silicon by way of an FPGA. I know that I will have to make a lot of adjustments in the input/output arena (the real world being different to the simulation environment) and have discovered that I did my design entirely in a program that doesn't export netlists or HDL code so all I really have is a schematic.

But, assuming that I somehow get to a point where I do have a netlist or HDL code of my design, what is my next step to get it into silicon? So far from what I've read it looks like FPGA's are my solution, but looking at the Xilinx and Altera websites makes my head spin. Am I barking up the wrong tree? Basically, I'm looking for a plain English description of what the next step is for a guy with a functional schematic of a CPU. Once I know what direction to go in, I can crack the books and figure out all I need to know about how to get there. Also a note, I am on Mac OS X but I have a Window's XP box that I can plug in if I absolutely have to.

  • \$\begingroup\$ What program did you do your design in? There may be 3rd party converters out there. \$\endgroup\$ Jul 25 '11 at 10:16

Congrats on your CPU design. Yes, the FPGA is definitely your next step. But you're not very clear what it is that makes your head spin. I presume it's the large number of different devices on offer. You also don't say what simulator you're using.
When you synthesize a design the synthesizer should give you a report on the resources used, like number of gates and RAM. This should give you an idea what parts are suitable for your design. Make sure you have enough headroom. Pick a part which has some extra RAM, which you'll need to execute programs on your CPU.

edit (re your comment)
You need a development system for a specific manufacturer. Altera and Xilinx are the big players, and both have their believers. Which one you choose is not that important, both have enough different parts to satisfy your needs.
If you would choose for Xilinx, it has its ISE WebPACK Design Software, which is free (large download at 3.4GB). The limitations compared to more advanced versions of the software shouldn't bother you at this time.
Next you need a development board. You need to have an idea of what FPGA you'll need to select one. If you go for Xilinx I would pick a Spartan, maybe a Spartan-6, the Virtex is already too high-end IMO. There's still a great many too choose from, mainly different in the extras on the board. You'll want a board with a bit more than a few switches and LEDs. I would look out for a keyboard connector, and a display module.
Xilinx has a number of boards, and for Xilinx FPGAs there's also Digilent, Avnet, Xess and many others.

So compare a number of boards (price will also play a part, I presume) and download the development software for the FPGA you plan to use. Synthesize your design to verify that it will fit in the chosen FPGA, and then you're ready to purchase a board around this FPGA.

I forgot to tell a bit about FPGAs. An FPGA is basically a large collection of gates with programmable connections between them, so that you can create almost any logic function/system with them. Over several generations FPGAs became more advanced and now have optimized blocks to create efficiently functions like RAM. Your development software's synthesizer creates the connection diagram between the gates. This isn't permanently stored in the FPGA, but must be loaded on power-up from an external configuration Flash memory. That's where your design will be stored. Like any other Flash memory it can be erased and rewritten a great number of times.

  • \$\begingroup\$ I used Logisim, which is fantastic for the schematics, but lacks a method of outputting anything but pictures (png, jpeg, etc.). On the FPGA confusions I have, its partly a matter of the vast array of devices, but also I don't find resources that explain the basics and fundamentals. If I put my CPU on there, how does it interface with the outside world? What equipment do I need? Can I re-program the FPGA repeatedly? etc. etc. etc. Its really just a total lack of familiarity with the subject. I guess I need a starter guide, but don't find one anywhere. \$\endgroup\$ Jul 25 '11 at 5:52
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    \$\begingroup\$ Your questions, in order: 1) FPGAs interface with the outside world via I/O pins. The difference is that you can choose the pins, unlike dedicated chips. 2) You can start with a starter kit, development kit, or similar. This will have the FPGA, some connectors for I/O, and power supplies on board. Most also include the programmer; if one doesn't don't forget to get one. 3) Yes, you can reprogram the FPGA. The program is stored on-chip in what is essentially a giant shift register. On startup, a dedicated state machine or external source loads it into the chip. \$\endgroup\$ Jul 25 '11 at 6:29

I'm not familiar with Xilinx's tools, but I am with Altera's, so I'll tell you about theirs. Xilinx and others shouldn't be too different.


The first thing you will need to do is learn Verilog. This will make your head hurt because Verilog (and the somewhat similar VHDL) was first designed as a simulation language, and many constructs (like #5 which means "wait 5 time steps", a time step usually being a nanosecond). So there are a lot of restrictions that you have to keep in mind to make your Verilog code synthesizable, i.e. compilable into a bitstream for an FPGA.

The biggest shock, though, is that what you write in Verilog (and VHDL) is the behavior you expect from the system, and the compiler infers the proper logic from your description. If you're not careful, you can get lots of nasty bugs from this.

For example, a D flip-flop looks like:

always @(posedge RESET or posedge CLK)
        Q <= 1'b0;
    else if(CLK_ENA)
        Q <= D;

This describes how a DFF works, and the compiler has to analyze it and figure out you want a DFF. The @(...) is called a sensitivity list, which is a list of signals that trigger a reevaluation of the code block; thus, in this block, Q only changes if there is a rising edge on RESET or CLK (this is for an active-high reset). If you forget something in the sensitivity list (which should contain all the right-hand-side variables without any posedge or negedge modifiers for a combinational logic block) the compiler will synthesize latches as needed rather than call an error. Crazy, but it's how it is, because Verilog was originally a simulation language that hid (and thus did not require) implementation details. VHDL is the same but much more verbose.

Finally, a new version of Verilog called SystemVerilog was released a few years back which makes writing synthesizable code much, much easier. If at all possible, learn this language, as Xilinx ISE and Altera Quartus II both support it. The main problem is the utter lack of good reference material.

The SystemVerilog version of a DFF cleans up a couple small things:

always_ff @(posedge RESET, posedge CLK)
        Q <= '0;
    else if(CLK_ENA)
        Q <= D;

Note that the signals in the sensitivity list are separated by commas. This is because or was confusing since and couldn't work there. Also note the replacement of 1'b0 (a single 0 bit) with '0 (a symbol that expands to however many 0 bits are needed based on what it is being assigned to; much more flexible with parameterized modules). Finally, note the replacement of always (which could be used for anything; combinational logic, latches, and flip flops) with always_ff which requires the contents to synthesize to flip-flops. There's also an always_comb which eliminates the sensitivity list, since it just works out the sensitivities from the inputs to the block.

Altera's design software is called Quartus II, and you'll be looking for the Web Edition. (The subscription editions are rather expensive and only needed for the fastest or most recent FPGA models.)

The sad part is that I haven't found a good book on the subject. What I've learned I got by piecing things together from multiple sources, such as Verilog books which don't do a good job of telling you what is synthesizable and what isn't, and example code. Quartus II has a "insert template" command that inserts template code for several common structures, from D flip-flops to state machines.

Demo Hardware

Once you've implemented your processor in Verilog, you need to build it. For the time being, let Quartus choose the chip (you have to choose the family; I'd recommend the Cyclone IV) and the pinouts. Once it biulds, you'll know how much chip you need. It will tell you how many logic elements, flip flops, RAM bits, etc. you used. Make sure you're not over 50% on any of those; if you are, look at the chip the compiler chose and manually select the next bigger (in logic elements) chip which has at least as many pins, and repeat until you get utilization under 50%.

Then go shopping for a demo board that has a chip at least as big as the one you finally built with. Check to see that it has the peripherals and/or I/O connectors that you'll need. It's not uncommon to build a daughtercard that plugs into an expansion connector to provide any missing hardware.

Now that you've picked your hardware, figure out the real pinouts and use the Pin Planner to put the right signals on the right pins. The demo board will have a user's guide that tells you which pins are wired to what devices or connector pins on the demo board.

Once you get the pinouts set, build it again so it uses the pins you want. Bear in mind that some signals like system clocks will need dedicated input pins (so they route straight to the internal PLLs).

Use the programmer to download your design directly into the FPGA (that shift register I mentioned a while back). Now you're in the familiar edit-compile-run debugging cycle. Beat on it until it works.

Once it works, you can use the programmer to download the code into the onboard configuration device so that your program will load and run on power-on.

This was pretty long, and I hope it helped some. There's a lot to learn; it's not like learning a new programming language as much as it's like learning a new programming paradigm, e.g. moving from procedural to functional languages. Verilog is a simultaneous language; most of the code is always executing.

Good luck!

  • \$\begingroup\$ Great, this very helpful. Just to check one thing though, I've heard about schematic capture. Is that a feasible alternative to learning verilog? I'll learn it if I have to, but if it's not 100% necessary I'd rather not add it to the enormous list of things I already need to figure out. Thanks much. \$\endgroup\$ Jul 25 '11 at 7:41
  • \$\begingroup\$ Honestly, not really. One big problem is that you're at the mercy of the schematic capture program: if it takes your schematic and generates incorrect Verilog, what can you do? Whereas writing Verilog will give you the needed authority to fix all the bugs. The big reason, though, is that there are things that schematic capture will never do as well as Verilog: Parameterized modules and bus splitting and merging are the ones that immediately jump to mind. \$\endgroup\$ Jul 25 '11 at 12:24
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    \$\begingroup\$ Are there any tools that can turn a somewhat more "hardware descriptive" language into Verilog or VHDL (e.g. if I want net Z to be a flip flop whose data input is a combination of A, B, and C, which is asynchronously reset while C and D are true, it would be nice to be able to say something like Z:= A & (B # C); Z.ar = C & D; without having to worry about sensitivity lists and such). \$\endgroup\$
    – supercat
    Jan 6 '12 at 17:02
  • \$\begingroup\$ Altera Quartus allows you to enter your design as a schematic or AHDL (Altera's version of VHDL), or any combination thereof, probably including other HDLs. (being old-fashioned, I primarily used schematic entry for my CPLD and FPGA projects, with a little AHDL.) \$\endgroup\$ Feb 5 '14 at 2:44
  • \$\begingroup\$ Just to be clear, AHDL is not a version of VHDL. Both VHDL and Verilog are inference languages, where your code describes the desired circuit's behavior, and the compiler has to infer the implementation from that behavioral description. This is a legacy of the fact that both started as simulation languages and were reused for synthesis. AHDL is a declarative language, where you declare primitives (e.g. flip-flops, truth tables), and how they're connected, so the compiler doesn't have to guess. AHDL dates back to the 80's and is much closer to ABEL. \$\endgroup\$ Feb 5 '14 at 18:48

Yes, FPGAs are almost certainly your solution!

You almost certainly will need to use one of the hardware description languages, or re-enter your schematics into a different tool. I'd recommend against the schematic approach as

  1. the FPGA tool vendors are not really supporting them well
  2. It's non-portable

Once you've written HDL, as long as you are not directly inserting things from the vendors library using their various "IP wizards" or by directly pasting in components from their libraries, you'll have code which you can port to other chips fairly easily (much more so than for example porting embedded C IME)

Also, you have a much better test and validation environment as you can write tests which "understand" your functionality and can check the results for you, rather than you staring at the waveforms to see if it all looks OK.

The big 2 HDLs are VHDL and Verilog. You might like to read this answer as to how they differ...

VHDL or Verilog?

I'd also say that MyHDL is also worth a look if you already know Python - gives you a huge verification ability, but still most of the low-level control that a "normal" HDL gives.

Once you choose an HDL, and then get that working (again, sorry!) in a simulation you'll then be in a state where you can push it through the vendor tools and learn the next large chunk of the task - once it simulate correctly, there's always more effort than you think getting it to synthesize :)

If you're wedded to schematics and can get a hold of a license, LabviewFPGA might suit you.


Get a copy of Rapid Prototyping of Digital Systems by Hamblen et al:


It mainly uses VHDL, which I prefer to Verilog.

It includes a very simple 8-bit CPU, the uP3, which I implemented on my own Altera FLEX 10K hardware some years ago, using an earlier edition of the book. I'll port it to this $25 Cyclone II board when I get my "front panel" PCB made. It also includes a MIPS and Altera NIOS II processor. You could work through the uP3 exercises in the book with the free Altera Quartus II tools, rewrite your CPU code in VHDL, and get it working on a Cyclone II board. Alternatively, Quartus II has schematic entry, and you should be able to input your schematic directly, simulate it, and run it on the Cyclone II.


If the difficulty is a steep learning curve with tools skills, then follow easiest path. Actel (now Microsemi) has Libero, the package of FPGA tools which require zero reading and are easy to start using: immediatelly after you have it installed. You can actually create schematics there by hand and with few clicks have it uploaded to physical FPGA, the screens on the way to do it are very self-explaining.


If you choose to learn an HDL, where you are may influence which is the better language. In Europe, VHDL is more popular. In USA, Verilog is more popular, except for defense industry which is VHDL. (USA department of defense originally created VHDL) That only means that people near you may be better able to help in one language or the other. But if you're looking for help online, then that may be irrelevant.

Other books to consider are Rapid Prototyping of Digital Systems: SOPC Edition which refers to the Altera DE1 and DE2 boards. There are already a number of different computers ported to DE1 and DE2, to give you ideas how they work. Minimigtg68 (Amiga), FpgaGen (Sega Genesis), etc. are ported to this board to have a look at for examples.

If you go Xilinx, there's two books I'm into right now. FPGA Prototyping By Verilog Examples: Xilinx Spartan-3 Version FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version Though I don't know a particular board to recommend with these. I am excited about a hopefully coming soon board, FPGA Arcade but I forget if it will have a Xilinx or something else.


Found this variant thats further developing Logisim, now called Logisim Evolution. They implemented a feature to export to VHDL from the schematics of a logic circuit built in logisim.

It can be found here: https://github.com/reds-heig/logisim-evolution

Know this question is old, but it helped me a heap, and hope it helps someone else.


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