I faced with some confusion in subject datasheet:

In one section PA.2 should be masking by PCIE1 bit as PA.2 is PCINT2 input and it should be within PCINT[7:0] and PCINT[15:12] range:

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On the other hand PA.2 (PCINT2) will generate Pin change interrupt 0:

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Is there something that I misunderstood? Or I just faced with a rare case of an error in documentation?


To be honest, errors in documentation aren't that rare, especially with companies that make tons of large documents.

In this case, my experience is that the register description and Pin-Package drawing are correct. As you should expect. Register interactions are documented during chip design, as is pin-out, whereas those tables are an after-though during or after testing.

I have not had problems with these exact chips going by register descriptions for the PCINTs (never use those tables) and I'm sure I have used PA2 for interrupts several times now, though I have used so many Atmels, it's all a bit of a blur.


Though seeing as the number of pins that are of different PCIE group is also not consistent on further look (2 mentioned in the table, 4 implied in the register description) I do advise a test. You-never-knows strong in this one are.


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