I'm following this tutorial: Lattice Diamond Hierarchical Design Test Bench Tutorial
However i am using Lattice Diamond ver. 3.4.1, and some details are different. The Problem i am facing is with the functions "Generate Schematic Symbol" and "VHDL Test Bench Template" found in the "Hierarchy" tab in the left Pane.
In both cases the generation fails with something similiar to the following message:
Generating Test Bench Template...
Starting: "source "F:/machx02/simulation_tutorial/hdle_generate_tbtemplate.tcl""
set parameters done
-- Analyzing VHDL file C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(28): ERROR: boolean is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(29): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(30): ERROR: string is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(31): ERROR: string is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(32): ERROR: boolean is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(36): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(37): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(38): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(39): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(42): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(46): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(47): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(48): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(49): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(52): ERROR: true is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(56): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(57): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(58): ERROR: std_logic is not declared (VHDL-1241)
C:/lscc/diamond/3.4_x64/cae_library/synthesis/vhdl/machxo2.vhd(59): ERROR: std_logic is not declared (VHDL-1241)
-- Sorry, too many errors..
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(35): ERROR: integer is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(38): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(39): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(40): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(41): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(42): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd(45): ERROR: unit dflipflop_nbit ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NBitDFF.vhd ignored due to errors (VHDL-1482)
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(33): ERROR: integer is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(36): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(37): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd(39): ERROR: unit nbitsatadder ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/NbitSatAdder.vhd ignored due to errors (VHDL-1482)
-- Analyzing VHDL file F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd (VHDL-1481)
-- Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb (VHDL-1493)
-- Restoring VHDL parse-tree std.standard from C:/lscc/diamond/3.4_x64/cae_library/vhdl_packages/vdbs/std/standard.vdb (VHDL-1493)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(32): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(33): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(34): ERROR: std_logic is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(35): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(36): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(37): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(38): ERROR: std_logic_vector is not declared (VHDL-1241)
F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd(40): ERROR: unit top_testbench_tutorial ignored due to previous errors (VHDL-1284)
-- VHDL file F:/machx02/simulation_tutorial/impl_lse/source/Top_Testbench_Tutorial.vhd ignored due to errors (VHDL-1482)
module top_testbench_tutorial is not found.
ERROR: Failed to generate test fixture template file.
Failed to Generate Test Bench Template.
If i do not try to generate the test bench template but use the code from the tutorial directly, the simulation works fine (starting the simuation wizard). Also if i start Synplify i can generate a schematic view.
Why is the compiler complaining about these types (std_logic etc..)
And why is "machx02.vhdl" even compiled, its not included in any source (the project is simulation only)
Any help appreciated!
