The performance benefit of a larger cache block size depends on the bandwidth and latency of main memory and the workload. If memory latency and bandwidth are relatively high (e.g., the first word is available in 8 processor cycles and an additional word every cycle), then if the workload is using even half of the cache block before it is evicted then a four-word block will increase performance (stalling only for 11 cycles instead of 16). (Since many memory technologies have burst constraints, the benefit might be less if the memory controller has a buffer [so sequential accesses might hit in the buffer, not suffering the full memory access penalty] or more if the misses are to different chunks of memory and using the full burst increases effective memory bandwidth].)
If the cache is writeback, the extra cost of eviction must be considered. For example, if 50% of the words are dirty, then the average stall (for the two accesses that on average hit in the 4-word block) would change from 16 cycles to 20 cycles and from 11 cycles to 19.25 cycles (75% of the blocks would be dirty since half of the words used are dirty and half of the words in a cache line are used).
A writeback cache with single-word blocks would also not need to read the memory for whole-word writes on a cache miss.
(Writethrough no-allocate has some advantages for direct-mapped caches, if there is a write buffer. Combining a write buffer and victim cache may be useful.)
In a direct mapped cache, increasing the block size will also increase the conflict miss rate.How significant this will be depends on the workload (and even on the mapping of data).
Other possible cache improvements include providing a victim cache (effectively a tiny L2 cache), using higher associativity (way prediction might be used to provide direct-mapped speed on correct predictions), and providing a prefetch buffer. If memory latency is significant, then there do not have to be many hits in a victim cache or prefetch buffer to compensate for delaying memory access. (Speculatively accessing memory on a miss before checking the victim cache/prefetch buffer would reduce latency for misses in these auxiliary caches, but it could increase latency when a victim cache hit is followed immediately by a victim cache miss since the second access might have to wait for the first to-be-discarded memory access completes before starting its own.)
Another possibility to consider is specialized caches. For example, if stack accesses can be filtered out from the rest of the data cache, then conflict misses would be reduced while keeping the simplicity of direct mapped caches.
Incidentally, some forms of way prediction benefit from larger-than-word cache blocks because they can exploit the locality of reference.