If the JFET is supplied from a constant current source (5ma flowing Source-Drain) Will changing the Vgs voltage do anything?
This Image for reference:
Another graph of a 2N5457 taken for the datasheet @ http://www.farnell.com/datasheets/666760.pdf
With reference to this Graph, same question although 0.5mA flowing Source-Drain.
If the current is fixed in the 2nd graph above at 0.5ma what Vgs range would cause the Vds to swing 0-2.5V?
Question title: JFET's Understanding - Voltage Controlled Resistor
Those graphs in the question are complete rubbish. This is what a JFET characteristic looks like in the positive Vds and Id quadrant: -
Between 0V and the pinch-off voltage is where we are interested. For a varying Vgs you should be able to see that there are several slopes (all fairly linear) that fairly reasonably can be said to be resistive.
For instance if you took the curve when Vgs = 0V, you can see that as Vds rises, Id also rises (as would a pure resistance of about 150 ohms. When Vgs = -2V, that resistance is about 500 ohms.
Other question: If the JFET is supplied from a constant current source (5ma flowing Source-Drain) Will changing the Vgs voltage do anything?
Yes, choose a value of Vgs and pick a point on its curve where the 5mA intercepts. Then go down to the base of the graph and note what that voltage is. For different values of Vgs a different Vds will result.
If the current is fixed in the 2nd graph above at 0.5ma what Vgs range would cause the Vds to swing 0-2.5V?
You won't find a value of Vgs that results in a Vd of zero volts - for this to happen the on-resistance of the JFET would have to be zero and this is not going to happen with any JFET.
JFET (N-channel) operation in ohmic region is described by the following relation:
\$ I_D = 2 K \left[ (V_{GS} - V_P) V_{DS} - \dfrac{V_{DS}^2}{2} \right] \qquad\qquad (0 < V_{DS} < V_{GS} - V_P) \$
where K is a constant depending on the fabrication process and \$V_P < 0\$ is the pinch-off voltage, i.e. the value of \$V_{GS}\$ for which the drain current becomes virtually zero.
Notice that the behaviour in that zone is not perfectly linear in \$i_{D}\$ vs. \$V_{DS}\$ (because of the quadratic term). If drain-souce voltage is much smaller than the overdrive voltage \$V_{GS} - V_P\$ then you can approximate that relation to a straight line. This accounts for the ohmic behavior.
In this situation the overdrive voltage (a.k.a. simply gate drive) sets the "resistance" of the JFET, i.e. the slope of the straight line. If you keep the drain current constant, changing \$V_{GS}\$ voltage will change the slope and therefore the corresponding \$V_{DS}\$ level.
The graphs you posted are usually too compressed to let you see any appreciable difference in slope in the ohmic region. Some JFET especially built to serve as variable resistors usually include an expanded graph of the ohmic region, i.e. the output characteristics of the JFET "zoomed in" where \$V_{DS}\$ is smallish (~5V max). In these graphs you can appreciate the different slopes.
