AC-coupling capacitors for high-speed differential interfaces

Question

Can you explain me why and where I should put AC-coupling capacitors (usually around 0.1uF) on high-speed (1...5 GHz) differential serial interfaces (like SerDes for Gigabit Ethernet SFP modules)?

From what I have read, the caps should be placed as close to receiver pins as possible. Any legit references are welcome.

[CHIP1 RX+]--||-------------[CHIP2 TX+]
[CHIP1 RX-]--||-------------[CHIP2 TX-]
            0.1uF


[CHIP1 TX+]-------------||--[CHIP2 RX+]
[CHIP1 TX-]-------------||--[CHIP2 RX-]
                       0.1uF

Thank you in advance

UPDATE:

Got a reply from the IC manufacturer and it advised me to put the caps closer to the transmitter. So it seems that the actual place depends on how the particular IC works. A while ago, there was a completely opposite advise from another manufacturer.

Answer 1

The coupling capacitors are usually placed close to the transmitter source.

Going along with Dr. Johnson, we need to figure out the distance. The propagation velocity of signals on most FR4 types of board is about c/2. This equates to around 170ps per inch for internal layers and more like 160 ps per inch for external layers.

Using a standard interface running at 2.5Gb/sec, the unit interval is 400ps, so according to that, we should be much less than 200 ps away from the transmitter. If this interface has been implemented in an IC, then you need to remember that the bond wires are part of this distance. Below is a slightly more in-depth look at the issue.

In practise, coupling devices are placed as close as possible to the transmitter device. This location naturally varies depending on the device.

Now the capacitor. This is an RLC device at these speeds, and most devices are well above self-resonance in multi-gigabit applications. This means you may well have a significant impedance that is higher than the transmission line.

For reference, the self inductance for a few device sizes: 0402 ~ 0.7nH 0603 ~ 0.9nH 0805 ~ 1.2nH

To get around high impedance device problems (a major issue in PCI express due to the nature of link training), we sometimes use so-called reverse geometry devices because the self inductance of the parts is significantly lower. Reverse geometry is just what it says: An 0402 device has the contacts 04 apart, where an 0204 device uses the 02 as the distance between the contacts. An 0204 part has a typical self inductance value of 0.3nH, significantly reducing the effective impedance of the device.

Now to that discontinuity: it will produce reflections. The further away that reflection, the larger the impact on the source (and energy loss, see below) within the distance range of 1/2 of the transition time of the signal; beyond that makes little difference.

At a distance of 1/2 the transition time or further from the source, the reflection can be calculated using the reflection coefficient equation ([Zl - Zs]/[Zl + Zs]). If the reflection is generated closer such that the effective reflection is lower than this, we have effectively reduced the reflection coefficient and reduced lost energy. The closer any known reflection may be situated with respect to the transmitter, the less effect on the system it will have. This is the reason that break-out vias under BGA devices with high speed interfaces is done as close to the ball as possible. It is all about reducing the effect of reflections.

As an example, if I place the coupling capacitor (for the 2.5Gb/sec link) at 0.1 inch from the source, then the distance equates to a time of 17ps. As the transition time of these signals is usually limited to no faster than 100 picoseconds, the reflection coefficient is therefore 17%. Note that this transition time equates to 5GHz signalling artefacts. If we place the device further away (beyond the transition time / 2 limit), and use the typical values for 0402 100nH, we have Z(cap) = 22 ohms, Z(track) about 50 ohms, and we therefore have a reflection coefficient of about 40%. The actual reflection will be worse due to the device pads.

Answer 2

Why would you add AC coupling capacitors to your high-speed signals? They add impedance discontinuities which can only hurt the signal integrity(?).

The REASON that AC coupling is used in high-speed signaling (USB3/PCIe/DisplayPort/...) is so that the IC manufacturers can have different power supplies that better fit their architecture.

For example, HDMI has 4 differential pairs. Each signal is terminated with 50 ohms to 5V. If you design an IC with HDMI, then you must also have a 5V supply. This is a serious pain-in-the-ass which adds additional cost and complexity.

DisplayPort uses AC coupling on the high speed signals so that each IC manufacturer can use what ever power supply best suits their needs.

AC coupling has its own set of challenges. In addition to the discontinuities that the AC coupling capacitor adds, there is usually some sort of initialization/balancing required (usually a string of 0's and 1's) to make sure that the DC offset is removed from the line before communication begins. Once communication begins care must be taken to keep the line balanced by sending the same number of 0's and 1's. (see 8b/10b encoding)

Answer 3

First why would you use AC coupling? From Dr Johnson here are three common reasons you might want to use them:

• To change the DC bias level when interconnecting logic families with different switching thresholds.
• To provide a removable interface that may be shorted to ground without damaging the output drivers.
• When combined with differential signaling and transformer coupling, to connect boxes without requiring any DC connection between the two product chassis.

The middle option is one of the main reasons we do this with removable pcie cards for example.

Now where to place. Any AC coupling capacitor that you place in your signal line is going to be a lower impedance point and will therefor cause a negative reflection back to the source. Whether or not this reflection will come back and then interfere with other bits is determined by the speed of your signal and the distance of this reflection point from your transmitter.

Again from another Johnson example he suggests that to avoid this ISI you should place your caps within "much less than 1/2 a baud interval". Given the example of a 10Gbps serdes link with a bit time of 100ps he suggests that would give a distance of less than 100mils. Then he further explains how you might reduce the parasitic capacitance of your caps and their low impedance reflection point.

Extending this line of thinking to 1.5Gbps with a bit time of 667ps that's a bit time of around 4 or 5 inches and taking a 10th of that gets you about half an inch. That seems fairly conservative to me but that's probably the point. In practice I've put blocking caps for pcie right on the connector but again I'm then lumping the reflection point of the caps in with the connector.

Your question is really related to transmission line theory and how reflections work. Reading up on that, perhaps doing some simulations if you have access to a tool, or a simple board experiment with caps at different locations should help you determine the best approach for your application.

Answer 4

1) You should first calculate the total impedance of the capacitor using formula:

ESR and ESL values are provided by manufacturers (or just use an impedance curve in a datasheet to find the impedance at the frequency of interest). A good low-ESL ceramic cap may have around 0.5 Ohm at 1 GHz.

2) If the value is much smaller then characteristic impedance of the line, it doesn't matter where you put it on the line: at the transmitter or the receiver.

When adding the capacitor near RX, if impedance is small, it is in series with the terminating resistor (or whatever it is at the RX) and should not materially affect signal integrity (50 Ohm + 0 Ohm = 50 Ohm).

3) Ideal location of the cap is at the TX, as the reflected signal will "add up" to the transmitted signal. While in case of positioning at the RX, the reflected signal may add up to a next symbol (depends on the time delay of a line) creating ISI.

---

So, in general, position requirements (at TX or RX) depends on the frequency of interest and total capacitor impedance at that frequency.

In you case, Z can be not much smaller than Z0. For 1 GHz, inductive reactance only may be around 6 Ohm (assuming 1 nH ESL, L*2*pi*f). So, for such high frequencies (1 GHz and above) the cap should be ideally located near TX, not near RX.

But for lower frequencies, when the capacitor impedance can be neglected (relative to Z0), the capacitor may be put at the RX side (as done sometimes in practice) w/o material damage to signal integrity.

UPDATE
For the case of "small" Z it is clear from above.

For the case of a "large" Z an enhanced rule would be:
- for a source termination place a coupling capacitor at the receiver.
- for a load termination place a coupling capacitor at the transmitter.
- for a load-source (dual) termination it doesn't matter.

In particular, for a case of source termination, recommendation to place a decoupling capacitor at the transmitter is wrong. Z is in series with Z0 (added to it). There is a direct negative impact on reflection. While if Z is at the receiver (assuming close to it), there is no negative effect (Z is added to some large load resistance, Z + infinity = infinity).